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21. 发明申请

US20070210412A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 有权
标题翻译：电气可编程PI形状的保险丝结构及其制造方法
公开(公告)号：US20070210412A1
公开(公告)日：2007-09-13
申请号：US11372380
申请日：2006-03-09
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

22. 发明申请

US20070117307A1 TRENCH MEMORY CELLS WITH BURIED ISOLATION COLLARS, AND METHODS OF FABRICATING SAME 有权
标题翻译：带有分离分离胶束的TRENCH记忆细胞及其制备方法
公开(公告)号：US20070117307A1
公开(公告)日：2007-05-24
申请号：US11164381
申请日：2005-11-21
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8244 , H01L29/94
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.
摘要翻译：本发明涉及半导体器件，优选动态随机存取存储器（DRAM）单元，每个单元包含至少一个具有埋入隔离环的沟槽电容器。沟槽电容器位于半导体衬底中的沟槽中，并且其包括内电极和外电极以及电介质层。埋入的隔离套环凹入沟槽的侧壁并且具有基本均匀的厚度。这种埋置的隔离环优选通过在沟槽蚀刻之前的氧注入形成。

23. 发明申请

US20070082437A1 Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby 有权
标题翻译：使用心轴制造半导体结构的方法和由此形成的半导体结构
公开(公告)号：US20070082437A1
公开(公告)日：2007-04-12
申请号：US11246830
申请日：2005-10-07
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.
摘要翻译：制造半导体结构的方法，其中在牺牲心轴的侧壁上形成单晶硅体，并通过该方法制造半导体结构。在形成单晶硅体之后，心轴的牺牲材料被选择性地去除到主体的单晶硅上。心轴可以由多孔硅组成，并且主体可以使用绝缘体上半导体衬底或块状衬底来制造。本体可用于制造翅片型场效应晶体管的翅片体。

24. 发明申请

US20070045698A1 Semiconductor structures with body contacts and fabrication methods thereof 审中-公开
标题翻译：具有身体接触的半导体结构及其制造方法
公开(公告)号：US20070045698A1
公开(公告)日：2007-03-01
申请号：US11216395
申请日：2005-08-31
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触晶圆。半导体本体包括用于垂直存储单元之一的存取装置的通道区域。延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

25. 发明申请

US20080050873A1 SEMICONDUCTOR STRUCTURES WITH BODY CONTACTS AND FABRICATION METHODS THEREOF 有权
标题翻译：具有身体接触的半导体结构及其制造方法
公开(公告)号：US20080050873A1
公开(公告)日：2008-02-28
申请号：US11928135
申请日：2007-10-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触晶圆。半导体本体包括用于垂直存储单元之一的存取装置的通道区域。延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

26. 发明申请

US20070090393A1 Gain cells and methods of making and using the same 有权
标题翻译：获得细胞及其使用方法
公开(公告)号：US20070090393A1
公开(公告)日：2007-04-26
申请号：US11259296
申请日：2005-10-26
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L29/74
CPC分类号： H01L27/10841 , G11C11/403 , G11C11/405 , H01L27/0207 , H01L27/10864 , H01L27/10894 , H01L29/045
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orientation of the NFET in the substrate is approximately perpendicular to the orientation of the PFET. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是基板的存储单元，其包括（1）具有与基板的表面近似平面的取向的PFET; 和（2）耦合到大致平面PFET的NFET。衬底中NFET的取向近似垂直于PFET的取向。提供了许多其他方面。

27. 发明申请

US20070069300A1 PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN 审中-公开
标题翻译：具有嵌入式源/漏极的平面超薄半导体绝缘体通道MOSFET
公开(公告)号：US20070069300A1
公开(公告)日：2007-03-29
申请号：US11162959
申请日：2005-09-29
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/2652 , H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

28. 发明申请

US20070210890A1 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US20070210890A1
公开(公告)日：2007-09-13
申请号：US11372387
申请日：2006-03-09
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

29. 发明申请

US20060284251A1 Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权
公开(公告)号：US20060284251A1
公开(公告)日：2006-12-21
申请号：US11155030
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

30. 发明申请

US20060284250A1 Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效
公开(公告)号：US20060284250A1
公开(公告)日：2006-12-21
申请号：US11154906
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

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