专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07078756B2 Collarless trench DRAM device 失效
标题翻译：无领沟槽DRAM器件
公开(公告)号：US07078756B2
公开(公告)日：2006-07-18
申请号：US10904933
申请日：2004-12-06
申请人： Yoichi Otani , Herbert L. Ho , Babar A. Khan , Paul C. Parries
发明人： Yoichi Otani , Herbert L. Ho , Babar A. Khan , Paul C. Parries
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.
摘要翻译：本发明提供了具有最小的垂直寄生FET泄漏的无凹槽沟槽半导体存储器件及其形成方法。

22. 发明申请

US20080064178A1 DEEP TRENCH CAPACITOR THROUGH SOI SUBSTRATE AND METHODS OF FORMING 有权
标题翻译：通过SOI衬底的深度电容器和形成方法
公开(公告)号：US20080064178A1
公开(公告)日：2008-03-13
申请号：US11470809
申请日：2006-09-07
申请人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
发明人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L29/945
摘要： Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
摘要翻译：公开了通过SOI衬底形成深沟槽电容器的方法和电容器。在一个实施例中，一种方法包括在SOI衬底中形成到硅衬底的沟槽开口; 在沟槽开口中沉积侧壁间隔物; 蚀刻以形成深沟槽进入硅衬底; 通过将掺杂剂注入硅衬底中形成第一电极，由此侧壁间隔件保护BOX层和硅层; 去除侧壁间隔物; 在深沟槽内沉积节点电介质; 以及通过在所述深沟槽中沉积导体而形成第二电极。植入可产生基本上均匀的深度掺杂区域，除了与深沟槽的最下部分相邻的部分，其可以是基本上是球状的。保护BOX层免受侧壁间隔物的底切，并且注入消除了对来自石英玻璃的扩散掺杂剂的需要。

23. 发明授权

US08053823B2 Simplified buried plate structure and process for semiconductor-on-insulator chip 有权
标题翻译：半导体绝缘体芯片的简化掩埋板结构和工艺
公开(公告)号：US08053823B2
公开(公告)日：2011-11-08
申请号：US10906808
申请日：2005-03-08
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L21/84 , H01L27/10864 , H01L27/10867 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.
摘要翻译：本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单一半导体区域的至少一部分。掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

24. 发明授权

US07575970B2 Deep trench capacitor through SOI substrate and methods of forming 有权
标题翻译：深沟槽电容器通过SOI衬底和成型方法
公开(公告)号：US07575970B2
公开(公告)日：2009-08-18
申请号：US11470809
申请日：2006-09-07
申请人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
发明人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
摘要翻译：公开了通过SOI衬底形成深沟槽电容器的方法和电容器。在一个实施例中，一种方法包括在SOI衬底中形成到硅衬底的沟槽开口; 在沟槽开口中沉积侧壁间隔物; 蚀刻以形成深沟槽进入硅衬底; 通过将掺杂剂注入硅衬底中形成第一电极，由此侧壁间隔件保护BOX层和硅层; 去除侧壁间隔物; 在深沟槽内沉积节点电介质; 以及通过在所述深沟槽中沉积导体而形成第二电极。植入可产生基本上均匀的深度掺杂区域，除了与深沟槽的最下部分相邻的部分，其可以是基本上是球状的。保护BOX层免受侧壁间隔物的底切，并且注入消除了对来自石英玻璃的扩散掺杂剂的需要。

25. 发明授权

US08372721B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08372721B2
公开(公告)日：2013-02-12
申请号：US13343850
申请日：2012-01-05
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

26. 发明授权

US08129797B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08129797B2
公开(公告)日：2012-03-06
申请号：US12141311
申请日：2008-06-18
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L27/088
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

27. 发明申请

US20120083092A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120083092A1
公开(公告)日：2012-04-05
申请号：US13323033
申请日：2011-12-12
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

28. 发明申请

US20120175694A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120175694A1
公开(公告)日：2012-07-12
申请号：US13408187
申请日：2012-02-29
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
摘要翻译：提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

29. 发明授权

US09059320B2 Structure and method of forming enhanced array device isolation for implanted plate EDRAM 有权
标题翻译：形成植入板EDRAM的增强阵列器件隔离的结构和方法
公开(公告)号：US09059320B2
公开(公告)日：2015-06-16
申请号：US13408187
申请日：2012-02-29
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L29/94 , H01L21/84 , H01L21/762 , H01L29/66
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
摘要翻译：提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

30. 发明授权

US08168507B2 Structure and method of forming enhanced array device isolation for implanted plate EDRAM 有权
标题翻译：形成植入板EDRAM的增强阵列器件隔离的结构和方法
公开(公告)号：US08168507B2
公开(公告)日：2012-05-01
申请号：US12545116
申请日：2009-08-21
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式