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21. 发明申请

US20120223386A1 Asymmetric FinFET devices 有权
标题翻译：非对称FinFET器件
公开(公告)号：US20120223386A1
公开(公告)日：2012-09-06
申请号：US13470393
申请日：2012-05-14
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L21/2633 , H01L21/26506 , H01L21/26586 , H01L29/517 , H01L29/785 , H01L29/7855 , H01L29/7856
摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
摘要翻译：公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角度进行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

22. 发明授权

US08242560B2 FinFET with thin gate dielectric layer 有权
标题翻译： FinFET具有薄栅介质层
公开(公告)号：US08242560B2
公开(公告)日：2012-08-14
申请号：US12688347
申请日：2010-01-15
申请人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.
摘要翻译：提供了一种半导体器件，其在一个实施例中包括在电介质表面之上的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区，漏区存在于半导体鳍结构的相对端。具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。至少一个栅极导体层与高k栅极电介质层直接接触。还提供了一种形成上述装置的方法。

23. 发明申请

US20120061762A1 Asymmetric FinFET devices 有权
公开(公告)号：US20120061762A1
公开(公告)日：2012-03-15
申请号：US12881152
申请日：2010-09-13
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/2633 , H01L21/26506 , H01L21/26586 , H01L29/517 , H01L29/785 , H01L29/7855 , H01L29/7856
摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

24. 发明申请

US20100301417A1 DEVICE INCLUDING HIGH-K METAL GATE FINFET AND RESISTIVE STRUCTURE AND METHOD OF FORMING THEREOF 有权
标题翻译：包括高K金属栅极FinFET和电阻结构的器件及其形成方法
公开(公告)号：US20100301417A1
公开(公告)日：2010-12-02
申请号：US12471872
申请日：2009-05-26
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/06 , H01L29/78 , H01L21/336
CPC分类号： H01L27/1211 , H01L27/0629 , H01L27/1203 , H01L29/517
摘要： A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric layer in the second region of the substrate. The semiconductor device may include a semiconductor body and a gate structure, in which the gate structure includes a gate dielectric material present on the semiconducting body and a metal gate material present on the gate dielectric material. The resistive structure may include semiconductor material having a lower surface is in direct contact with the dielectric layer in the second region of the substrate. The resistive structure may be a semiconductor containing fuse or a polysilicon resistor. A method of forming the aforementioned device is also provided.
摘要翻译：提供了一种器件，其在一个实施例中包括具有第一区域和第二区域的衬底，其中半导体器件存在于衬底的第一区域中的电介质层上，并且电阻结构存在于介电层中第二区域。半导体器件可以包括半导体本体和栅极结构，其中栅极结构包括存在于半导体本体上的栅极电介质材料和存在于栅极电介质材料上的金属栅极材料。电阻结构可以包括具有下表面的半导体材料与衬底的第二区域中的电介质层直接接触。电阻结构可以是包含半导体的熔丝或多晶硅电阻器。还提供了一种形成上述装置的方法。

25. 发明授权

US08889562B2 Double patterning method 有权
标题翻译：双重图案化方法
公开(公告)号：US08889562B2
公开(公告)日：2014-11-18
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

26. 发明授权

US08343877B2 Angle ion implant to re-shape sidewall image transfer patterns 有权
标题翻译：角度离子注入重新形成侧壁图像传输模式
公开(公告)号：US08343877B2
公开(公告)日：2013-01-01
申请号：US12614952
申请日：2009-11-09
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/28132 , H01L21/26586 , H01L29/66787
摘要： A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.
摘要翻译：一种用于制造集成电路的特征的方法及其装置包括在半导体器件的表面上形成第一结构并在第一结构的周围形成间隔物。将角度离子注入施加到器件，使得间隔物具有来自成角度离子注入的保护部分和未受保护部分，其中未保护部分具有大于被保护部分的蚀刻速率的蚀刻速率。相对于受保护部分，非保护部分和第一结构被选择性地去除。将间隔物的受保护部分下面的层图案化以形成集成电路特征。

27. 发明授权

US08324036B2 Device having and method for forming fins with multiple widths for an integrated circuit 有权
标题翻译：具有用于形成用于集成电路的多个宽度的散热片的装置和方法
公开(公告)号：US08324036B2
公开(公告)日：2012-12-04
申请号：US12614986
申请日：2009-11-09
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

28. 发明申请

US20120256261A1 SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120256261A1
公开(公告)日：2012-10-11
申请号：US13083879
申请日：2011-04-11
申请人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
IPC分类号： H01L29/772 , H01L21/31
CPC分类号： H01L21/28123 , H01L21/76224 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
摘要翻译：一种半导体器件，包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

29. 发明授权

US08263446B2 Asymmetric FinFET devices 有权
标题翻译：非对称FinFET器件
公开(公告)号：US08263446B2
公开(公告)日：2012-09-11
申请号：US12881152
申请日：2010-09-13
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L21/2633 , H01L21/26506 , H01L21/26586 , H01L29/517 , H01L29/785 , H01L29/7855 , H01L29/7856
摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
摘要翻译：公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角执行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

30. 发明授权

US08003455B2 Implantation using a hardmask 有权
标题翻译：使用硬掩模进行植入
公开(公告)号：US08003455B2
公开(公告)日：2011-08-23
申请号：US12469710
申请日：2009-05-21
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/266 , H01L21/823892
摘要： A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
摘要翻译：公开了一种用于处理CMOS阱的方法，并且使用单个硬掩模执行多个离子注入。该方法包括在基板上形成和图案化硬掩模，由此硬掩模获得第一开口。衬底可以是半导体衬底。该方法还包括执行第一离子注入，其间在第一开口外部，硬掩模基本上防止离子到达衬底。该方法还涉及以光致抗蚀剂覆盖硬掩模的方式施加光致抗蚀剂，并且其还填充第一开口。然后使用光致抗蚀剂来模拟硬掩模，由此硬掩模获得第二开口。该方法还包括执行第二离子注入，其间在第二开口外部，填充第一开口的硬掩模和光致抗蚀剂基本上防止离子到达衬底。两个离子注入可用于形成两种类型的CMOS阱。

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