专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07671647B2 Apparatus and method for trimming static delay of a synchronizing circuit 有权
标题翻译：用于修整同步电路的静态延迟的装置和方法
公开(公告)号：US07671647B2
公开(公告)日：2010-03-02
申请号：US11341774
申请日：2006-01-26
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： H03L7/06
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03L7/0812
摘要： A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an input clock signal path and a feedback clock signal is provided from the feedback clock signal path and an input clock signal is provided from the input clock signal path for phase comparison. For trimming a duty cycle of first and second output clock signals, one of a first delayed input clock signal and a second delayed input clock signal is delayed. The first and second delayed input clock signals are complementary. The delayed clock signal and the other clock signal are provided as the first and second output clock signals.
摘要翻译：一种用于修整延迟锁定环（DLL）的未经调整的前向延迟并修剪由DLL提供的第一和第二输出时钟信号的占空比的系统和方法。为了调整未调整的正向延迟，将延迟添加到反馈时钟信号路径和输入时钟信号路径之一，并且从反馈时钟信号路径提供反馈时钟信号，并且从输入时钟信号路径提供输入时钟信号进行相位比较。为了调整第一和第二输出时钟信号的占空比，第一延迟输入时钟信号和第二延迟输入时钟信号之一被延迟。第一和第二延迟输入时钟信号是互补的。延迟的时钟信号和另一个时钟信号被提供为第一和第二输出时钟信号。

22. 发明申请

US20090316496A1 INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY 有权
标题翻译：具有可调输出驱动能力的输入输出线路感测放大器
公开(公告)号：US20090316496A1
公开(公告)日：2009-12-24
申请号：US12549200
申请日：2009-08-27
申请人： Kang Yong Kim , Chulmin Jung
发明人： Kang Yong Kim , Chulmin Jung
IPC分类号： G11C7/10 , G11C8/00 , G11C7/02
CPC分类号： G11C7/1096 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/4091 , G11C11/4097 , G11C13/004 , H03F3/16
摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.
摘要翻译：输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制读出放大器的输出驱动。

23. 发明授权

US07567465B2 Power saving sensing scheme for solid state memory 有权
标题翻译：固态存储器的省电感测方案
公开(公告)号：US07567465B2
公开(公告)日：2009-07-28
申请号：US11847559
申请日：2007-08-30
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.
摘要翻译：公开了诸如涉及固态存储器件的方法和装置。一种这样的方法包括选择存储器阵列中的多个存储器单元。确定存储在所选择的多个存储单元中的多个数据位的状态。在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。顺序提供多个数据位作为输出。在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

24. 发明授权

US07514954B2 Method and apparatus for output driver calibration 有权
标题翻译：输出驱动器校准的方法和装置
公开(公告)号：US07514954B2
公开(公告)日：2009-04-07
申请号：US11432421
申请日：2006-05-10
申请人： Kang Yong Kim , Jeffrey P. Wright
发明人： Kang Yong Kim , Jeffrey P. Wright
IPC分类号： H03K17/16 , H03K19/003 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1069 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by generating a first variable count in response to comparing a reference voltage to a first voltage at a calibration terminal when an external load is connected. A first pull-up impedance circuit is varied in response to a first variable count and varying an impedance in a second variable pull-up impedance circuit in response to the first variable count. A second variable count is generated responsive to comparing the reference voltage to a second voltage at a reference node between the second variable pull-up impedance circuit and is serially connected to a variable pull-down impedance circuit. The impedance to the variable pull-down impedance circuit is varied in response to the second variable count. The first and second variable counts for configuring the output drivers are output when a steady state is achieved.
摘要翻译：输出驱动器校准电路确定用于配置可调阻抗输出驱动器的校准值。当外部负载连接时，响应于将参考电压与校准端子处的第一电压进行比较，产生第一变量计数来校准输出驱动器。第一上拉阻抗电路响应于第一可变计数而变化，并响应于第一可变计数改变第二可变上拉阻抗电路中的阻抗。响应于将参考电压与第二可变上拉阻抗电路之间的参考节点处的第二电压进行比较并且串联连接到可变下拉阻抗电路而产生第二变量计数。可变下拉阻抗电路的阻抗响应于第二可变计数而变化。当实现稳定状态时，输出用于配置输出驱动器的第一个和第二个变量计数。

25. 发明授权

US07421606B2 DLL phase detection using advanced phase equalization 有权
标题翻译：使用高级相位均衡的DLL相位检测
公开(公告)号：US07421606B2
公开(公告)日：2008-09-02
申请号：US10848261
申请日：2004-05-18
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： G06F1/04 , G06F1/12 , G06F1/14 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： H03L7/0814 , H03L7/085
摘要： A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit. The avoidance of wrong ForceSL exit and On1x overshooting problems further results in faster DLL locking time.
摘要翻译：公开了一种在同步电路（例如延迟锁定环或DLL）的初始化期间产生和终止时钟移位模式的系统和方法。在初始化时，DLL进入ForceSL（左移强制）模式和一个1 x模式（即在每个时钟周期左移）。在将粗略相位检测器应用于粗略相位检测窗口之前，跟踪基准时钟的相位（反过来来自系统时钟）的反馈时钟最初在粗略相位检测器中被延迟。反馈时钟的两个延迟版本由参考时钟采样，以产生一对相位信息信号，然后将其用于建立高级相位相等（APHEQ）信号。 APHEQ信号提前启动PHEQ（相位均衡）阶段，并用于终止ForceSL和On 1 x模式，从而防止在On 1 x退出时由于时钟抖动或反馈路径过冲引起的错误的ForceSL退出。避免错误的ForceSL退出和On 1 x超调问题进一步导致更快的DLL锁定时间。

26. 发明授权

US07327173B2 Delay-locked loop having a pre-shift phase detector 有权
标题翻译：具有预移相相位检测器的延迟锁定环路
公开(公告)号：US07327173B2
公开(公告)日：2008-02-05
申请号：US11344988
申请日：2006-01-31
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.
摘要翻译：一种时钟发生器，用于产生与具有第一和第二可调延迟线的输入时钟信号同步的输出时钟信号。在初始化时钟发生器之后，调整第一个可调延迟线，以便在初始化之后获得锁定条件。第二可调延迟线在与第一可调延迟线实现同步或第一可调延迟线达到最大可调延迟之后被调整。当最初获得锁定条件时，第一可调延迟线被重置，并且第二可调延迟线被调整以补偿第一可调延迟线的复位。

27. 发明授权

US06292420B1 Method and device for automatically performing refresh operation in semiconductor memory device 有权
标题翻译：用于在半导体存储器件中自动执行刷新操作的方法和装置
公开(公告)号：US06292420B1
公开(公告)日：2001-09-18
申请号：US09604300
申请日：2000-06-26
申请人： Kang Yong Kim , Saeng Hwan Kim , Jong Hee Han
发明人： Kang Yong Kim , Saeng Hwan Kim , Jong Hee Han
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： The present invention discloses a method and a device for automatically performing a refresh operation, which can reduce power consumption in an auto refresh mode of a semiconductor memory device. The power consumption can be reduced by controlling the operation of input buffers or the operation of an input buffer generator for controlling the input buffers, during the auto refresh operation. The device for automatically performing the refresh operation in the semiconductor memory device, includes: a plurality of input buffers; an input buffer generator for controlling the operation of the plurality of input buffers; a command decoder for decoding a signal from one input buffer among the plurality of input buffers, and generating an auto refresh signal; a row active generator for generating a row active signal as the auto refresh signal is enabled; a delay generator for generating a delay signal delayed as long as a RAS cycle time according to the row active signal; and an auto refresh generator for controlling the plurality of input buffers by employing a control signal decided by the combination of the auto refresh signal from the command decoder and the delay signal from the delay generator.
摘要翻译：本发明公开了一种自动执行刷新操作的方法和装置，其可以降低半导体存储器件的自动刷新模式中的功耗。在自动刷新操作期间，通过控制输入缓冲器的操作或用于控制输入缓冲器的输入缓冲发生器的操作，能够降低功耗。用于在半导体存储器件中自动执行刷新操作的装置包括：多个输入缓冲器; 用于控制多个输入缓冲器的操作的输入缓冲器发生器; 命令解码器，用于对来自多个输入缓冲器中的一个输入缓冲器的信号进行解码，并产生自动刷新信号; 用于在启用自动刷新信号时产生行有源信号的行有源发生器; 延迟发生器，用于根据行有效信号产生延迟RAS周期时间的延迟信号; 以及自动刷新发生器，用于通过采用由命令解码器的自动刷新信号和来自延迟发生器的延迟信号的组合决定的控制信号来控制多个输入缓冲器。

28. 发明授权

US08587354B2 Control of a variable delay line using line entry point to modify line power supply voltage 有权
公开(公告)号：US08587354B2
公开(公告)日：2013-11-19
申请号：US13171755
申请日：2011-06-29
申请人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
发明人： Tyler Gomm , Kang Yong Kim , Jongtae Kwak
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.

29. 发明授权

US08271823B2 DLL phase detection using advanced phase equalization 有权
标题翻译：使用高级相位均衡的DLL相位检测
公开(公告)号：US08271823B2
公开(公告)日：2012-09-18
申请号：US12228771
申请日：2008-08-15
申请人： Kang Yong Kim
发明人： Kang Yong Kim
IPC分类号： G06F1/12 , G06F13/42
CPC分类号： H03L7/0814 , H03L7/085
摘要： A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit. The avoidance of wrong ForceSL exit and On1x overshooting problems further results in faster DLL locking time.
摘要翻译：公开了一种在同步电路（例如延迟锁定环或DLL）的初始化期间产生和终止时钟移位模式的系统和方法。初始化时，DLL将进入ForceSL（强制左移）模式和On1x模式（即，每个时钟周期左移）。在将粗略相位检测器应用于粗略相位检测窗口之前，跟踪基准时钟的相位（反过来来自系统时钟）的反馈时钟最初在粗略相位检测器中被延迟。反馈时钟的两个延迟版本由参考时钟采样，以产生一对相位信息信号，然后将其用于建立高级相位相等（APHEQ）信号。 APHEQ信号进入PHEQ（相位均衡）阶段的开始，并用于终止ForceSL和On1x模式，从而防止在On1x退出时由于时钟抖动或反馈路径过冲引起的错误的ForceSL退出。避免错误的ForceSL退出和On1x超调问题进一步导致更快的DLL锁定时间。

30. 发明申请

US20120182059A1 SEAMLESS COARSE AND FINE DELAY STRUCTURE FOR HIGH PERFORMANCE DLL 有权
标题翻译：高性能DLL的无缝粗糙和精细延迟结构
公开(公告)号：US20120182059A1
公开(公告)日：2012-07-19
申请号：US13341418
申请日：2011-12-30
申请人： Jongtae Kwak , Kang Yong Kim
发明人： Jongtae Kwak , Kang Yong Kim
IPC分类号： H03K5/159
CPC分类号： H03L7/00 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：时钟同步系统和方法避免了高频时的输出时钟抖动，并且在粗略和精细延迟的边界处实现了平滑的相位转变。系统可以使用配置成从输入参考时钟产生两个中间时钟并且在它们之间具有固定的相位差的延迟线。相位混合器接收这两个中间时钟并产生具有在中间时钟的相位之间的相位的最终输出时钟。在高时钟频率下在延迟线上的移位不影响馈入相位混频器的中间时钟之间的相位关系。来自相位混频器的输出时钟与输入参考时钟同步，即使在高时钟频率输入时也不会出现任何抖动或噪音。由于管理摘要的规则，本摘要不应用于解释索赔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式