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21. 发明申请

US20100095094A1 METHOD FOR PROCESSING DATA 审中-公开
标题翻译：数据处理方法
公开(公告)号：US20100095094A1
公开(公告)日：2010-04-15
申请号：US12640201
申请日：2009-12-17
申请人： Martin VORBACH , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
发明人： Martin VORBACH , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
IPC分类号： G06F9/30
CPC分类号： G06F8/45 , G06F15/7867
摘要： A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
摘要翻译：一种用于将程序转换为包括至少一个第一处理器和可重构单元的系统的方法和装置。确定适合于可重构单元的程序的代码部分。程序的剩余代码被提取和/或分离以供第一处理器处理。

22. 发明授权

US07657877B2 Method for processing data 有权
标题翻译：数据处理方法
公开(公告)号：US07657877B2
公开(公告)日：2010-02-02
申请号：US10480003
申请日：2002-06-20
申请人： Martin Vorbach , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
发明人： Martin Vorbach , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
IPC分类号： G06F9/44
CPC分类号： G06F8/45 , G06F15/7867
摘要： A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
摘要翻译：一种用于将程序转换为包括至少一个第一处理器和可重构单元的系统的方法和装置。确定适合于可重构单元的程序的代码部分。程序的剩余代码被提取和/或分离以供第一处理器处理。

23. 发明申请

US20090031104A1 Low Latency Massive Parallel Data Processing Device 审中-公开
标题翻译：低延迟大量并行数据处理设备
公开(公告)号：US20090031104A1
公开(公告)日：2009-01-29
申请号：US11883670
申请日：2006-02-06
申请人： Martin Vorbach , Frank May
发明人： Martin Vorbach , Frank May
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F9/38 , G06F9/30014 , G06F9/30058 , G06F9/3842 , G06F9/3867 , G06F9/3885 , G06F15/7867
摘要： Data processing device comprising a multidimensional array of ALUs, having at least two dimensions where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array.
摘要翻译：数据处理设备包括多维ALU阵列，其具有维度中的ALU的数量大于或等于2的至少两个维度，适于在相应阵列中的ALU中的至少一些ALU之间处理没有寄存器的数据引起的等待时间。

24. 发明授权

US07266725B2 Method for debugging reconfigurable architectures 有权
标题翻译：调试可重构架构的方法
公开(公告)号：US07266725B2
公开(公告)日：2007-09-04
申请号：US09967497
申请日：2001-09-28
申请人： Martin Vorbach , Frank May , Armin Nückel
发明人： Martin Vorbach , Frank May , Armin Nückel
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G06F9/30036 , G06F11/267 , G06F11/3656 , G06F15/7867
摘要： A method for efficiently debugging a program defining a plurality of configurations to be successively processed on a dynamically reconfigurable architecture including a plurality of logic elements cooperating with each other. The method includes storing data in a memory in a configuration-conforming manner, the data generated by executing a configuration forming part of the program on the reconfigurable architecture, and including algorithmically relevant state data of the program that is associated with at least one of the configurations. The method further includes subsequently continuing execution of the program, the execution including a reconfiguration, and detecting an error based on stored state data, wherein for each state for which corresponding state data is to be stored, the state remains unchanged at least until the corresponding state data is stored. For obtaining a particular state data, the method interrupts execution of the program by configuring a first configuration via which the particular state data is transmitted to a debugging unit instead of a second configuration that is a next-required configuration of the program; and subsequent to obtaining the particular state data, resumes execution of the program by configuring the second configuration.
摘要翻译：一种用于有效地调试定义要在包括彼此协作的多个逻辑元件的动态可重构架构上连续处理的多个配置的程序的方法。该方法包括以符合配置的方式将数据存储在存储器中，所述数据通过执行在所述可重构架构上形成所述程序的一部分的配置而生成，并且包括与所述程序的至少一个相关联的所述程序的与算法相关的状态数据配置该方法还包括随后继续执行程序，执行包括重新配置，并且基于存储的状态数据检测错误，其中对于要对其存储对应的状态数据的每个状态，状态至少保持不变，直到相应的状态数据被存储。为了获得特定状态数据，该方法通过配置将特定状态数据发送到调试单元而不是作为程序的下一个所需配置的第二配置的第一配置来中断程序的执行; 并且在获得特定状态数据之后，通过配置第二配置来恢复程序的执行。

25. 发明申请

US20120284630A1 Window Proxy 审中-公开
标题翻译：窗口代理
公开(公告)号：US20120284630A1
公开(公告)日：2012-11-08
申请号：US13461066
申请日：2012-05-01
申请人： Frank May
发明人： Frank May
IPC分类号： G06F3/01 , G06F15/16
CPC分类号： G06F9/542 , G06F2209/545
摘要： A preferably secured server, hosting a website, connected to the internet, interacting with a user's local machine by means of executing supplemental code in the form of a browser plug-in, with the intent of modifying the capabilities of a conventional internet browser beyond its initially designed capacity, thus relieving the web designer of the limitations imposed by the original browser source code. The browser plug-in executes a process that is run in conjunction with the browser application, enabling the viewer application/process of the present invention to broadcast unrestricted code and UI elements from the local computer's operating system, and presenting the user with robust, interactive applications, framed within the current browsing application window, thus streamlining the user's experience, and providing the appearance of a secure web application, despite the reality that the browser is merely framing the complex application within the browser.
摘要翻译：优选安全的服务器，托管连接到互联网的网站，通过以浏览器插件的形式执行补充代码与用户的本地机器交互，目的是修改超出其的常规互联网浏览器的能力最初设计的容量，从而减轻了网页设计师原始浏览器源代码所施加的限制。浏览器插件执行与浏览器应用程序一起运行的进程，使得本发明的查看器应用/处理能够从本地计算机的操作系统广播无限制的代码和UI元素，并向用户呈现鲁棒的，互动的应用程序，构建在当前浏览应用程序窗口内，从而简化用户的体验，并提供安全的Web应用程序的外观，尽管浏览器只是在浏览器中构建复杂的应用程序。

26. 发明授权

US08301872B2 Pipeline configuration protocol and configuration unit communication 有权
标题翻译：管道配置协议和配置单元通信
公开(公告)号：US08301872B2
公开(公告)日：2012-10-30
申请号：US11122500
申请日：2005-05-04
申请人： Martin Vorbach , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
发明人： Martin Vorbach , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
IPC分类号： G06F12/00
CPC分类号： G06F15/7867 , G06F9/3885 , G06F9/3897
摘要： An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the first configuration word. The method also includes transmitting a second configuration word to the first processing unit. The method also includes transmitting a reconfiguration signal to the first unit, the reconfiguration signal indicating that the first unit should begin processing data in accordance with the second configuration word. If the first processing unit has completed processing data in accordance with the first configuration word prior to when the reconfiguration signal is received by the first processing unit, data may be processed by the first processing unit in accordance with the second configuration word. If the first processing unit has not completed processing data in accordance with the first configuration word, data may continue to be processed with the first processing unit in accordance with the first configuration word.
摘要翻译：一种控制具有蜂窝结构的数据处理系统的示例性方法。该方法包括将第一配置字发送到蜂窝结构中的第一处理单元。该方法还包括根据第一配置字与第一处理单元处理数据。该方法还包括将第二配置字发送到第一处理单元。该方法还包括向第一单元发送重新配置信号，该重新配置信号指示第一单元应当根据第二配置字开始处理数据。如果第一处理单元在第一处理单元接收到重新配置信号之前已经完成了根据第一配置字的处理数据，则可以由第一处理单元根据第二配置字处理数据。如果第一处理单元没有根据第一配置字完成处理数据，则可以根据第一配置字继续使用第一处理单元处理数据。

27. 发明申请

US20110271264A1 METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURES 有权
标题翻译：翻译可重构建筑方案的方法
公开(公告)号：US20110271264A1
公开(公告)日：2011-11-03
申请号：US13177820
申请日：2011-07-07
申请人： Martin VORBACH , Frank May , Armin Nückel
发明人： Martin VORBACH , Frank May , Armin Nückel
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Data processing using multidimensional fields is described along with methods for advantageously using high-level language codes.
摘要翻译：描述使用多维字段的数据处理以及有利地使用高级语言代码的方法。

28. 发明授权

US07840842B2 Method for debugging reconfigurable architectures 有权
标题翻译：调试可重构架构的方法
公开(公告)号：US07840842B2
公开(公告)日：2010-11-23
申请号：US11890094
申请日：2007-08-03
申请人： Martin Vorbach , Frank May , Armin Nückel
发明人： Martin Vorbach , Frank May , Armin Nückel
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G06F9/30036 , G06F11/267 , G06F11/3656 , G06F15/7867
摘要： A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger.
摘要翻译：描述了一种用于调试可重配置硬件的方法。在一个示例实施例中，将调试信息写入每个配置周期到存储器中，然后由调试器对其进行评估。

29. 发明申请

US20100070671A1 METHOD AND DEVICE FOR PROCESSING DATA 有权
标题翻译：用于处理数据的方法和设备
公开(公告)号：US20100070671A1
公开(公告)日：2010-03-18
申请号：US12621860
申请日：2009-11-19
申请人： Martin VORBACH , Frank May , Armin Nuckel
发明人： Martin VORBACH , Frank May , Armin Nuckel
IPC分类号： G06F13/14
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： In a system including a multidimensional field of reconfigurable elements, and a method for operating said field of reconfigurable elements, one or more groups of said elements suitable for processing a predetermined task may be determined, a particular one of the one or more groups is selected, and the selected group is configured in a predetermined manner during runtime for processing the predetermined task, and in manufacturing of said system.
摘要翻译：在包括可重构元件的多维场的系统以及用于操作所述可重构元件的场的方法中，可以确定适于处理预定任务的一个或多个所述元件组，选择一个或多个组中的特定一个组，并且在运行时间期间以预定方式配置所选择的组以处理预定任务，以及在所述系统的制造中。

30. 发明授权

US07595659B2 Logic cell array and bus system 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US07595659B2
公开(公告)日：2009-09-29
申请号：US10398546
申请日：2001-10-08
申请人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： H03K19/177 , G06F7/52 , G06F15/00
CPC分类号： H03K19/17796 , G06F15/7867
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

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