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21. 发明申请

US20090146223A1 PROCESS AND METHOD TO LOWER CONTACT RESISTANCE 审中-公开
标题翻译：降低接触电阻的方法和方法
公开(公告)号：US20090146223A1
公开(公告)日：2009-06-11
申请号：US11950574
申请日：2007-12-05
申请人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
发明人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
IPC分类号： H01L29/94 , H01L21/8236
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/808 , H01L29/812
摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.
摘要翻译：一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加更多的杂质）。然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。之后，在栅极导体的侧壁上形成永久的间隔物。然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。

22. 发明授权

US08551845B2 Structure and method for increasing strain in a device 有权
标题翻译：增加器件应变的结构和方法
公开(公告)号：US08551845B2
公开(公告)日：2013-10-08
申请号：US12886903
申请日：2010-09-21
申请人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
发明人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26566 , H01L21/26593 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.
摘要翻译：公开了用于增加器件中应变的方法和结构，特别是n型场效应晶体管（NFET）互补金属氧化物半导体（CMOS）器件。本发明的实施例包括生长外延层，进行冷碳或簇碳预非晶化注入以将取代碳注入到外延层中，在外延层上形成拉伸帽，然后退火以使非晶层重结晶以产生应力记忆技术（SMT）效应。因此，外延层将包括取代碳并具有由SMT引起的记忆拉伸应力。本发明的实施例还可以包括在外延层下面的下部外延层，下部外延层包括例如硅碳磷（SiCP）层。

23. 发明授权

US08361847B2 Stressed channel FET with source/drain buffers 有权
标题翻译：具有源极/漏极缓冲器的强调通道FET
公开(公告)号：US08361847B2
公开(公告)日：2013-01-29
申请号：US13009029
申请日：2011-01-19
申请人： Jeffrey B. Johnson , Ramachandran Muralidhar , Philip J. Oldiges , Viorel C. Ontalus , Kai Xiu
发明人： Jeffrey B. Johnson , Ramachandran Muralidhar , Philip J. Oldiges , Viorel C. Ontalus , Kai Xiu
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
摘要翻译：用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。

24. 发明申请

US20110212587A1 ASYMMETRIC SOURCE AND DRAIN STRESSOR REGIONS 有权
公开(公告)号：US20110212587A1
公开(公告)日：2011-09-01
申请号：US13099406
申请日：2011-05-03
申请人： Jeffrey B. Johnson , Viorel C. Ontalus
发明人： Jeffrey B. Johnson , Viorel C. Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/6653 , H01L29/66659 , H01L29/7848
摘要： A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.

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