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21. 发明授权

US06747447B2 Locking apparatus and loadboard assembly 失效
标题翻译：锁定装置和装载板组件
公开(公告)号：US06747447B2
公开(公告)日：2004-06-08
申请号：US10254401
申请日：2002-09-25
申请人： Niels Markert , Anthony Le , Robert Sauer , Rochit Rajsuman , Hiroki Yamoto
发明人： Niels Markert , Anthony Le , Robert Sauer , Rochit Rajsuman , Hiroki Yamoto
IPC分类号： G01R3102
CPC分类号： G01R31/2886
摘要： The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved. Based on the profile of the cam slots, the loadboard assembly can be gradually lowered to achieve contact between the printed circuit board and the contact pins on the test head and to lock the interface board.
摘要翻译：本发明涉及半导体测试装置装置的锁定装置和装载板组件。装载板组件包括包含被测器件的印刷电路板和固定到印刷电路板底部的接口板。接口板有两个成员之间有空格。隔板连接构件以形成测试头上的接触针的孔。装载板组件放置在安装在测试头的顶表面上的锁定装置的顶部上。装载板在锁定装置上的布置根据延伸穿过接合板和装载板组件的印刷电路板中的两个孔的不同横截面的两个销进行。当将装载板组件放置在锁定机构上时，安装在接口板上的辊被容纳在锁定装置的凸轮构件的凸轮槽中。当凸轮构件移动时，这些滚轮跟随凸轮槽。基于凸轮槽的轮廓，可以逐渐降低装载板组件以实现印刷电路板与测试头上的接触针之间的接触并锁定接口板。

22. 发明授权

US09697872B2 High speed serial peripheral interface memory subsystem 有权
公开(公告)号：US09697872B2
公开(公告)日：2017-07-04
申请号：US13313699
申请日：2011-12-07
申请人： Kevin Widmer , Anthony Le , Cliff Zitlaw
发明人： Kevin Widmer , Anthony Le , Cliff Zitlaw
IPC分类号： G06F13/00 , G11C5/02 , G06F13/42 , G06F13/16
CPC分类号： G11C5/02 , G06F13/1694 , G06F13/4291
摘要： A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component where data is accessed on leading and falling edges of a clock signal.

23. 发明授权

US09223726B2 Apparatus and method for programmable read preamble with training pattern 有权
标题翻译：具有训练模式的可编程读取前导码的装置和方法
公开(公告)号：US09223726B2
公开(公告)日：2015-12-29
申请号：US12879936
申请日：2010-09-10
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F3/00 , G06F12/16 , G11C16/00 , G08B5/22 , G06F11/10 , G11C7/22 , H04L7/04 , G06F1/12
CPC分类号： G06F12/16 , G06F1/12 , G06F11/10 , G08B5/222 , G11C5/066 , G11C7/1006 , G11C7/222 , G11C11/5621 , G11C16/00 , H04L7/04
摘要： A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.
摘要翻译：提供存储器件。该存储器件包括前置码存储器和存储器控制器。前导码存储器被布置为存储读取前导码，使得读取前导码包括适合于对准用于读取数据的捕获点的训练模式。此外，训练模式是可编程的，使得训练模式可以在制造前同步码存储器之后至少改变一次。响应于读取命令，存储器控制器提供存储在前导码存储器中的读取前导码以及读取的数据。

24. 发明授权

US08417874B2 High speed memory having a programmable read preamble 有权
标题翻译：具有可编程读取前置码的高速存储器
公开(公告)号：US08417874B2
公开(公告)日：2013-04-09
申请号：US12691633
申请日：2010-01-21
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C7/1072 , G11C7/20
摘要： The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
摘要翻译：主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式，其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式，其中在高速存储器上电之后加载默认前导码模式。可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。另外，可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。

25. 发明授权

US07437589B2 Providing precise timing control within a standardized test instrumentation chassis 失效
标题翻译：在标准化的测试仪器底盘内提供精确的时序控制
公开(公告)号：US07437589B2
公开(公告)日：2008-10-14
申请号：US11197022
申请日：2005-08-03
申请人： Anthony Le , Glen Gomes
发明人： Anthony Le , Glen Gomes
IPC分类号： G06F1/12
CPC分类号： G01R31/31716 , G01R31/31715 , G01R31/31726
摘要： Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
摘要翻译：通过在PXI_LOCAL上提供多个控制信号，可以获得标准化机箱（如PXI）内的精确时序控制。最低共通信号（LCM）信号使所有时钟在每个LCM边沿都具有一致的时钟边沿。启动顺序允许测试系统中的所有PXI扩展卡同时启动。一个MATCH线使PIN卡模块能够检查预期的DUT输出，并继续执行本地测试程序或回送并根据DUT输出检查的结果重复本地测试程序的一部分。如果pincard模块中的本地测试程序检测到错误，则测试结束（EOT）线可以使任何一个pincard模块突然结束在所有其他pincard模块中运行的本地测试程序。

26. 发明授权

US07437588B2 Circuit card synchronization within a standardized test instrumentation chassis 失效
标题翻译：标准化测试仪器底盘内的电路卡同步
公开(公告)号：US07437588B2
公开(公告)日：2008-10-14
申请号：US11196996
申请日：2005-08-03
申请人： Anthony Le , Glen Gomes
发明人： Anthony Le , Glen Gomes
IPC分类号： G06F1/12
CPC分类号： G01R31/31725 , G01R31/31726
摘要： Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
摘要翻译：通过在PXI_LOCAL上提供多个控制信号，可以获得标准化机箱（如PXI）内的精确时序控制。最低共通信号（LCM）信号使所有时钟在每个LCM边沿都具有一致的时钟边沿。启动顺序允许测试系统中的所有PXI扩展卡同时启动。一个MATCH线使PIN卡模块能够检查预期的DUT输出，并继续执行本地测试程序或回送并根据DUT输出检查的结果重复本地测试程序的一部分。如果pincard模块中的本地测试程序检测到错误，则测试结束（EOT）线可以使任何一个pincard模块突然结束在所有其他pincard模块中运行的本地测试程序。

27. 发明授权

US07171602B2 Event processing apparatus and method for high speed event based test system 失效
标题翻译：基于高速事件的测试系统的事件处理设备和方法
公开(公告)号：US07171602B2
公开(公告)日：2007-01-30
申请号：US10318959
申请日：2002-12-13
申请人： Glen Gomes , Anthony Le
发明人： Glen Gomes , Anthony Le
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31937 , G01R31/318328 , G01R31/31919 , G01R31/31922
摘要： An apparatus and method for computing event timing for high speed event based test system. The event processing apparatus includes an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period and a fraction of the clock period, an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form, and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic. The events in the event data are specified as groups of events where each group of event is configured by one base event and at least one companion event.
摘要翻译：一种用于计算基于高速事件的测试系统的事件定时的装置和方法。事件处理装置包括事件存储器，用于存储每个事件的事件数据，其中事件数据包括形成有时钟周期和时钟周期的一部分的整数倍的每个事件的定时数据，用于累加事件的事件加法逻辑定时数据并且以并行形式产生累积的定时数据，以及事件发生器，用于基于从事件求和逻辑以并行形式接收的累积定时数据生成由事件数据指定的事件。事件数据中的事件被指定为事件组，每组事件由一个基本事件和至少一个随播事件配置。

28. 发明授权

US07010452B2 Event pipeline and summing method and apparatus for event based test system 失效
标题翻译：事件流水线和基于事件的测试系统的求和方法和装置
公开(公告)号：US07010452B2
公开(公告)日：2006-03-07
申请号：US10618387
申请日：2003-07-12
申请人： Glen Gomes , Anthony Le
发明人： Glen Gomes , Anthony Le
IPC分类号： G06F11/00
CPC分类号： G01R31/31922 , G01R31/31917 , G01R31/31928 , G01R31/31932
摘要： An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.
摘要翻译：用于基于高速事件的测试系统的事件管线和游标求和装置处理事件数据以高速度的各种定时产生驱动事件和选通事件以评估被测半导体器件。事件流水线和游标求和装置由事件计数延迟逻辑，游标数据解压缩逻辑，事件游标求和逻辑，事件缩放逻辑和窗口选通逻辑来配置。本发明的事件管线和求和方法和装置被设计成使用流水线结构执行高速事件定时处理。窗口选通逻辑提供用于检测窗口选通请求并产生窗口选通使能的功能。

29. 发明授权

US06771062B1 Apparatus for supporting and manipulating a testhead in an automatic test equipment system 失效
标题翻译：用于在自动测试设备系统中支撑和操纵测试头的设备
公开(公告)号：US06771062B1
公开(公告)日：2004-08-03
申请号：US10438364
申请日：2003-05-14
申请人： Niels Markert , Anthony Le , Robert Sauer
发明人： Niels Markert , Anthony Le , Robert Sauer
IPC分类号： G01R104
CPC分类号： G01R31/2887
摘要： An apparatus for supporting and manipulating a testhead for testing semiconductor devices includes a supporting frame, plates adapted to be mounted on opposite sides of the testhead and controllable shafts that connect the supporting frame to the plates. Each plate has an opening in which a flanged bearing is fitted. The testhead is mounted by moving the respective shafts through the flanged bearings within the openings of plates. In this manner, the shafts support the testhead on two fixed pivots. The shafts also provide a fixed axis of rotation about which the testhead can be rotated. The testhead can be locked in a particular position about the fixed rotation axis by a locking pin inserted into one of a plurality of locking holes surrounding the plate opening. A lever arm connected to the locking pin is utilized to change the radial position of the testhead. The testhead is dismounted by unlocking the locking pin and moving the shafts from the flanged bearings.
摘要翻译：用于支撑和操纵用于测试半导体器件的测试头的装置包括支撑框架，适于安装在测试头的相对侧上的板和将支撑框架连接到板的可控轴。每个板都有一个开口，其中安装有法兰的轴承。通过将相应的轴移动通过板的开口内的凸缘轴承来安装测试头。以这种方式，轴在两个固定的枢轴上支撑测试头。这些轴还提供固定的旋转轴线，围绕其旋转测试头。通过插入到围绕板开口的多个锁定孔中的一个中的锁定销，test头可以围绕固定的旋转轴线被锁定在特定位置。连接到锁定销的杠杆臂用于改变测头的径向位置。通过解锁锁定销并从法兰轴承上移动轴来拆卸test头。

30. 发明授权

US06668331B1 Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory 失效
标题翻译：用于连续产生事件以建立大于可由事件存储器中的指定数据位表示的总延迟时间的装置和方法
公开(公告)号：US06668331B1
公开(公告)日：2003-12-23
申请号：US09535031
申请日：2000-03-24
申请人： Glen A. Gomes , Anthony Le , James Alan Turnquist , Rochit Rajusman , Shigeru Sugamori
发明人： Glen A. Gomes , Anthony Le , James Alan Turnquist , Rochit Rajusman , Shigeru Sugamori
IPC分类号： G06F104
CPC分类号： G01R31/31922 , G01R31/31921
摘要： An apparatus and method in an event based test system for testing an electronics device under test (DUT). The apparatus includes an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and an additional delay time inserted in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The additional delay time is inserted by replicating the timing data and the event type data of the event immediately prior to the specified event.
摘要翻译：用于测试被测电子设备（DUT）的基于事件的测试系统中的装置和方法。该装置包括用于存储每个事件的定时数据和事件类型数据的事件存储器，其中当前事件的定时数据由来自使用指定数量的数据位之前的事件的延迟时间表示，并且附加延迟时间插入到指定事件的定时数据中，以建立当前事件的总延迟时间，该延迟时间长于事件存储器中指定数量的数据位可表示的总延迟时间。通过在指定事件之前复制事件的定时数据和事件类型数据来插入附加的延迟时间。

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