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21. 发明授权

US09268720B2 Load balancing scheme in multiple channel DRAM systems 有权
标题翻译：多通道DRAM系统中的负载均衡方案
公开(公告)号：US09268720B2
公开(公告)日：2016-02-23
申请号：US12872282
申请日：2010-08-31
申请人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1647 , G06F12/0607 , G06F13/1642 , G06F13/1657 , G06F2213/0064
摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.
摘要翻译：多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。内存通道的访问由内存控制器控制。总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

22. 发明申请

US20120054455A1 Non-Uniform Interleaving Scheme In Multiple Channel DRAM System 审中-公开
标题翻译：多通道DRAM系统中的非均匀交织方案
公开(公告)号：US20120054455A1
公开(公告)日：2012-03-01
申请号：US12872458
申请日：2010-08-31
申请人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号： G06F12/06
CPC分类号： G06F13/1647 , G06F12/0607
摘要： A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.
摘要翻译：多通道DRAM系统中的非均匀交织方案包括将存储器数据与存储器地址相关联，将地址区域与预定范围的存储器地址相关联，并将预定的交织粒度与地址区域相关联。存储器数据在两个或更多个存储器通道之间交错，使得预定的交织粒度被应用于每个地址区。

23. 发明授权

US08502373B2 3-D integrated circuit lateral heat dissipation 有权
标题翻译： 3-D集成电路横向散热
公开(公告)号：US08502373B2
公开(公告)日：2013-08-06
申请号：US12115076
申请日：2008-05-05
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/3732 , H01L23/3735 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/01019
摘要： By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.
摘要翻译：通过在层叠的IC器件的层之间填充导热材料，在一个层内的一个或多个位置处产生的热可以横向移位。热的横向位移可以沿着层的整个长度，并且热材料可以是电绝缘的。通过硅通孔（TSV）可以在某些位置构建，以帮助散热的位置。

24. 发明申请

US20120061804A1 Systems and Methods for Enabling Esd Protection on 3-D Stacked Devices 有权
标题翻译：在3-D堆叠设备上启用Esd保护的系统和方法
公开(公告)号：US20120061804A1
公开(公告)日：2012-03-15
申请号：US13298884
申请日：2011-11-17
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L25/065 , H01L21/98
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

25. 发明授权

US08125040B2 Two mask MTJ integration for STT MRAM 有权
标题翻译：两个掩模MTJ集成为STT MRAM
公开(公告)号：US08125040B2
公开(公告)日：2012-02-28
申请号：US12405461
申请日：2009-03-17
申请人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
发明人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层上沉积，第一电极，固定磁化层，隧道势垒层，自由磁化层和第二电极。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二电介质钝化层覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

26. 发明授权

US08080862B2 Systems and methods for enabling ESD protection on 3-D stacked devices 有权
标题翻译：用于在3-D堆叠器件上实现ESD保护的系统和方法
公开(公告)号：US08080862B2
公开(公告)日：2011-12-20
申请号：US12206914
申请日：2008-09-09
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/58
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

27. 发明申请

US20100059869A1 Systems and Methods for Enabling ESD Protection on 3-D Stacked Devices 有权
标题翻译：在3-D堆叠器件上实现ESD保护的系统和方法
公开(公告)号：US20100059869A1
公开(公告)日：2010-03-11
申请号：US12206914
申请日：2008-09-09
申请人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
发明人： Kenneth Kaskoun , Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/52 , H01L21/50 , H02H9/04 , H01L23/538
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/60 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01093 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
摘要翻译：在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。

28. 发明申请

US20100038801A1 Corrosion Control of Stacked Integrated Circuits 有权
标题翻译：堆叠集成电路的腐蚀控制
公开(公告)号：US20100038801A1
公开(公告)日：2010-02-18
申请号：US12192514
申请日：2008-08-15
申请人： Shiqun Gu , Matthew Nowak
发明人： Shiqun Gu , Matthew Nowak
IPC分类号： H01L23/20 , H01L21/58
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.
摘要翻译：一种系统和方法可以防止腐蚀性元件（或至少氧化剂）在层叠IC器件的两层之间的界面处与金属连接接触。当层彼此靠近地定位时，在层的平面表面的边界处形成空腔。该空腔由层之间的周边密封界定。在一个实施例中，在空腔内产生真空，从而减小空腔内的腐蚀性气氛。在另一个实施例中，空腔填充惰性气体，例如氩气。一旦腔体的氧化元件减少，外围密封件就可以被密封，以防止污染物进入腔体中。

29. 发明申请

US20090261437A1 Two Mask MTJ Integration For STT MRAM 有权
标题翻译：两个掩模MTJ集成为STT MRAM
公开(公告)号：US20090261437A1
公开(公告)日：2009-10-22
申请号：US12405461
申请日：2009-03-17
申请人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
发明人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
IPC分类号： H01L43/00 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层上沉积，第一电极，固定磁化层，隧道势垒层，自由磁化层和第二电极。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二电介质钝化层覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

30. 发明申请

US20120154333A1 CAPACITIVE MEMS-BASED DISPLAY WITH TOUCH POSITION SENSING 审中-公开
标题翻译：具有触摸位置感测功能的基于MEMS的电容显示器
公开(公告)号：US20120154333A1
公开(公告)日：2012-06-21
申请号：US13404526
申请日：2012-02-24
申请人： Shiqun Gu , Matthew Nowak
发明人： Shiqun Gu , Matthew Nowak
IPC分类号： G06F3/045
CPC分类号： G06F3/0412 , G06F3/044
摘要： A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage.
摘要翻译：用于显示和触摸位置感测的微电子机械系统（MEMS）像素包括基板和电容元件。电容元件包括一个或多个像素，其具有在衬底上方的第一导电片，以及在第一导电片上方并与第一导电片形成间隔开的第二导电片，所述两片片形成电容元件。与每个血小板的连接提供施加电压，其中血小板分离根据所施加的电压而改变。与衬底间隔开并与衬底相对设置的透明电介质板覆盖至少一个像素。附接到与像素的每个血小板的连接的电容感测电路感测不是由施加电压引起的电容变化。

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