专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07782693B2 Semiconductor memory device and operation control method thereof 有权
标题翻译：半导体存储器件及其操作控制方法
公开(公告)号：US07782693B2
公开(公告)日：2010-08-24
申请号：US12007518
申请日：2008-01-11
申请人： Byoung-Sul Kim , Joon-Hee Lee , Jae-in Song , Jun-Ho Jo
发明人： Byoung-Sul Kim , Joon-Hee Lee , Jae-in Song , Jun-Ho Jo
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C7/1042 , G11C11/4076
摘要： A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.
摘要翻译：提供半导体存储器件及其操作控制方法。该方法可以包括执行控制，使得响应于一个预先活动命令可以连续执行预充电操作模式和主动操作模式，从而减少系统的电流消耗和负载，从而提高系统性能。

22. 发明授权

US07719375B2 Automatically calibrating frequency features of a phase locked loop 有权
标题翻译：自动校准锁相环的频率特征
公开(公告)号：US07719375B2
公开(公告)日：2010-05-18
申请号：US11745654
申请日：2007-05-08
申请人： Seong-Hwan Cho , Kyung-Lok Kim , Jung-Hyup Lee , Joon-Hee Lee
发明人： Seong-Hwan Cho , Kyung-Lok Kim , Jung-Hyup Lee , Joon-Hee Lee
IPC分类号： H03B1/00
CPC分类号： H04B1/46
摘要： A PLL includes an open-loop automatic frequency calibration circuit. The open-loop automatic frequency calibration circuit includes a frequency detector, first and second sinks, a comparator and a bank selector. The frequency detector generates an up-signal and a down-signal responding to a frequency difference between a first phase difference signal having a phase difference from a reference oscillation signal and the second phase difference signal having a phase difference from a frequency division oscillation signal. The first and second sinks discharge the first and second capacitors respectively responding to the up-signal and the down-signal. The comparator compares voltages of the first and second capacitors. The bank selector selects a bank according to binary search, selects an optimum bank among two banks lastly searched, and outputs a bank selection signal. The voltage-controlled oscillation changes frequency features thereof in response to the bank selection signal.
摘要翻译： PLL包括开环自动频率校准电路。开环自动频率校准电路包括频率检测器，第一和第二吸收器，比较器和组选择器。频率检测器响应于具有与参考振荡信号的相位差的第一相位差信号与具有与分频振荡信号的相位差的第二相位差信号之间的频率差产生上升信号和下降信号。第一和第二吸收器分别响应于上信号和下信号而放电第一和第二电容器。比较器比较第一和第二电容器的电压。银行选择器根据二进制搜索选择银行，最后在两个银行中选择一个最优库，并输出存款单元选择信号。电压控制振荡响应于存储体选择信号改变其频率特征。

23. 发明授权

US07589022B2 Method of chemical mechanical polishing and method of fabricating semiconductor device using the same 失效
标题翻译：化学机械抛光方法及使用其制造半导体器件的方法
公开(公告)号：US07589022B2
公开(公告)日：2009-09-15
申请号：US11585713
申请日：2006-10-24
申请人： Hyun-Suk Kim , Won-Jin Kim , Joon-Hee Lee , Yong-Seok Kim , Jong-Won Kim
发明人： Hyun-Suk Kim , Won-Jin Kim , Joon-Hee Lee , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L27/105 , H01L27/11526 , H01L27/11531
摘要： There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.
摘要翻译：提供了化学机械抛光（CMP）的方法和使用其的半导体器件的制造方法。该方法包括在包括正常抛光区域和碟形区域的半导体衬底上形成待抛光层，并且在可能发生凹陷的区域中在待抛光层上形成凹陷（即，过抛光） - 预防层。然后，使用防止凹陷层防止要抛光的层，同时使其抛光。因此，在可能发生凹陷（即，过度抛光）的区域中形成凹陷防止层，从而防止在图案密度低的区域和图案尺寸在该过程中发生凹陷的CMP。

24. 发明申请

US20090037784A1 Semiconductor memory device having mount test circuits and mount test method thereof 失效
标题翻译：具有安装测试电路及其安装测试方法的半导体存储器件
公开(公告)号：US20090037784A1
公开(公告)日：2009-02-05
申请号：US12219815
申请日：2008-07-29
申请人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
发明人： Byoung-Sul Kim , Joon-Hee Lee , Kwan-Yong Jin , Seung-Hee Lee
IPC分类号： G11C29/08 , G06F11/00
CPC分类号： G11C29/28 , G11C29/40 , G11C2029/4002
摘要： A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.
摘要翻译：提供一种具有安装测试电路及其安装测试方法的半导体存储器件。用于包括多个存储块的半导体存储器件的测试电路可以包括：比较单元，用于比较从多个存储块中选出的至少两个存储块的测试数据，判断所选择的存储器的测试数据块相同，并输出通过信号或失败信号作为标志信号; 以及输出选择单元，用于选择所选择的存储器块中的任何一个作为输出存储器块，并且每当从比较单元产生故障信号时改变输出存储器块，从而将其形成为可以减少误差的数据输出路径发生。

25. 发明申请

US20080176072A1 Enamel Varnish Composition For Enamel Wire And Enamel Wire Using The Same 有权
标题翻译：搪瓷漆漆组合物用于搪瓷线和搪瓷线使用它
公开(公告)号：US20080176072A1
公开(公告)日：2008-07-24
申请号：US11816785
申请日：2005-05-27
申请人： Joon-Hee Lee
发明人： Joon-Hee Lee
IPC分类号： B32B27/34 , C08L79/08
CPC分类号： H01B3/305 , C08K5/34926 , C08L79/08 , C08L2205/02 , C09D179/08 , H01B3/306 , Y10T428/2933 , C08L2666/20
摘要： Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin, presented in the Chemistry FIG. 1; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost insulated coating layer contacted with the conducting wire, shows the increased adhesivity of the insulated coating layer to the conducting wire without forming an additional bonding layer, as well as the excellent physical properties such as the wear resistance and flexibility, etc.
摘要翻译：公开了用于搪瓷丝的搪瓷清漆组合物和使用其的搪瓷丝。本发明涉及搪瓷丝的搪瓷清漆组合物，其中在有机溶剂中包含聚合物树脂组分，其中聚合物树脂组分包括第一聚酰胺酰亚胺树脂，呈现在化学图 1; 和具有聚酰胺酰亚胺的第二树脂，其中三嗪环被引入主链。将这种涂料颜料组合物施加到与导线接触的最内层绝缘涂层的漆包线显示出绝缘涂层对导线的粘附性增加而不形成另外的粘合层，以及优异的物理性能如耐磨性和柔韧性等。

26. 发明申请

US20070264951A1 METHODS OF AUTOMATICALLY CALIBRATING FREQUENCY FEATURES OF A PHASE LOCKED LOOP, AND PHASE LOCKED LOOPS INCLUDING AN OPEN-LOOP AUTOMATIC FREQUENCY CALIBRATION CIRCUIT 有权
标题翻译：自动校准相位锁定环路的频率特性的方法和包括开环自动频率校准电路的相位锁定机架
公开(公告)号：US20070264951A1
公开(公告)日：2007-11-15
申请号：US11745654
申请日：2007-05-08
申请人： Seong-Hwan Cho , Kyung-Lok Kim , Jung-Hyup Lee , Joon-Hee Lee
发明人： Seong-Hwan Cho , Kyung-Lok Kim , Jung-Hyup Lee , Joon-Hee Lee
IPC分类号： H04B1/18
CPC分类号： H04B1/46
摘要： A PLL includes an open-loop automatic frequency calibration circuit. The open-loop automatic frequency calibration circuit includes a frequency detector, first and second sinks, a comparator and a bank selector. The frequency detector generates an up-signal and a down-signal responding to a frequency difference between a first phase difference signal having a phase difference from a reference oscillation signal and the second phase difference signal having a phase difference from a frequency division oscillation signal. The first and second sinks discharge the first and second capacitors respectively responding to the up-signal and the down-signal. The comparator compares voltages of the first and second capacitors. The bank selector selects a bank according to binary search, selects an optimum bank among two banks lastly searched, and outputs a bank selection signal. The voltage-controlled oscillation changes frequency features thereof in response to the bank selection signal.
摘要翻译： PLL包括开环自动频率校准电路。开环自动频率校准电路包括频率检测器，第一和第二吸收器，比较器和组选择器。频率检测器响应于具有与参考振荡信号的相位差的第一相位差信号与具有与分频振荡信号的相位差的第二相位差信号之间的频率差产生上升信号和下降信号。第一和第二吸收器分别响应于上信号和下信号而放电第一和第二电容器。比较器比较第一和第二电容器的电压。银行选择器根据二进制搜索选择银行，最后在两个银行中选择一个最优库，并输出一个存款单元选择信号。电压控制振荡响应于存储体选择信号改变其频率特征。

27. 发明授权

US09640549B2 Vertical memory device with gate lines at the same level connected 有权
公开(公告)号：US09640549B2
公开(公告)日：2017-05-02
申请号：US14534181
申请日：2014-11-06
申请人： Seok-Won Lee , Joon-Hee Lee , Dong-Seog Eun , Chang-Hyun Lee
发明人： Seok-Won Lee , Joon-Hee Lee , Dong-Seog Eun , Chang-Hyun Lee
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11556 , G11C5/06 , H01L27/11548 , H01L27/11575 , G11C8/14 , H01L29/66 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , G11C5/063 , G11C8/14 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

28. 发明授权

US07592665B2 Non-volatile memory devices having floating gates 失效
标题翻译：具有浮动门的非易失性存储器件
公开(公告)号：US07592665B2
公开(公告)日：2009-09-22
申请号：US11594327
申请日：2006-11-08
申请人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
发明人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。还讨论了相关方法。

29. 发明申请

US20090072322A1 SEMICONDUCTOR DEVICES INCLUDING LINE PATTERNS SEPARATED BY CUTTING REGIONS 有权
标题翻译：半导体器件，包括切割区域划分的线形图案
公开(公告)号：US20090072322A1
公开(公告)日：2009-03-19
申请号：US11961551
申请日：2007-12-20
申请人： Sung-Bok Lee , Joon-Hee Lee
发明人： Sung-Bok Lee , Joon-Hee Lee
IPC分类号： H01L27/105
CPC分类号： H01L27/11568 , H01L27/0207 , H01L27/115
摘要： Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.
摘要翻译：提供半导体器件。半导体器件可以包括衬底和在基板上的彼此平行的第一方向上延伸的多个虚拟线图案。虚线图案中的每一个可以包括沿着第一方向排列的多个子线图案，并且通过其间的至少一个切割区域彼此分离。假线图案可以包括在垂直于第一方向的第二方向上彼此相邻的第一和第二假线图案。第一伪线图案的一对子线图案之间的切割区域中的至少一个与第二虚线图案的第二方向上的一条子线图案对准并限定在第二方向上。

30. 发明授权

US07246280B2 Memory module with parallel testing 失效
标题翻译：内存模块并行测试
公开(公告)号：US07246280B2
公开(公告)日：2007-07-17
申请号：US11086059
申请日：2005-03-22
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.
摘要翻译：存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X个测试数据位。存储器模块包括多个存储器芯片和多个比较单元。每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个测试数据位。此外，每个比较单元从相应的存储器芯片内的一个存储器块输出测试数据位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式