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21. 发明授权

US07313050B2 Word-line driver for memory devices 有权
标题翻译：用于内存设备的字线驱动程序
公开(公告)号：US07313050B2
公开(公告)日：2007-12-25
申请号：US11406984
申请日：2006-04-18
申请人： Cheng Hung Lee , Hung-Jen Liao
发明人： Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designating an output of the first inverter and an input of the second inverter, the first inverter having a NMOS transistor with a controllable first source, and a first pull-up circuitry coupled between a positive supply voltage and the first node and selectively activated by a first control signal, wherein when the first source is set to the positive supply voltage and the first control signal is set to a complementary supply voltage of the positive supply voltage, the first node is pulled up to the positive supply voltage to ensure an output of the second inverter is pulled down to the complementary supply voltage.
摘要翻译：字线驱动器具有来自字线解码器的输入和用于驱动字线的输出。字线驱动器包括串联连接在输入和输出之间的多个反相器，包括具有指定第一反相器的输出的第一节点和第二反相器的输入的第一和第二反相器，第一反相器具有NMOS 具有可控第一源的晶体管，以及耦合在正电源电压和第一节点之间并由第一控制信号选择性地激活的第一上拉电路，其中当第一源被设置为正电源电压和第一控制信号设定为正电源电压的互补电源电压，将第一节点上拉至正电源电压，以确保将第二逆变器的输出下拉至互补电源电压。

22. 发明授权

US07215587B2 Tracking circuit for a memory device 有权
公开(公告)号：US07215587B2
公开(公告)日：2007-05-08
申请号：US11172873
申请日：2005-07-05
申请人： Cheng Hung Lee , Simon Wang , Hung-Jen Liao
发明人： Cheng Hung Lee , Simon Wang , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C7/22 , G11C7/227 , G11C11/419
摘要： A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.

23. 发明授权

US09153302B2 Memory and method of operating the same 有权
标题翻译：内存和操作方法相同
公开(公告)号：US09153302B2
公开(公告)日：2015-10-06
申请号：US13362847
申请日：2012-01-31
申请人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
发明人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
IPC分类号： G11C7/00 , G11C7/12 , G11C7/18 , G11C11/419
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.
摘要翻译：存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。每个存储块包括一对位线和耦合到该对位线的多个存储器单元。每个全局位线耦合到至少一个存储器块。预充电电路被配置为将全局位线一次一个地预充电到预充电电压。选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。

24. 发明授权

US08659090B2 Resistive memory and methods for forming the same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US08659090B2
公开(公告)日：2014-02-25
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

25. 发明申请

US20130161707A1 Resistive Memory and Methods for Forming the Same 有权
标题翻译：电阻记忆及其形成方法
公开(公告)号：US20130161707A1
公开(公告)日：2013-06-27
申请号：US13335569
申请日：2011-12-22
申请人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
发明人： Chia-En Huang , Wun-Jie Lin , Ling-Chang Hu , Hsiao-Lan Yang , Chih-Chieh Chiu , Wei-Shuo Kao , Hong-Chen Cheng , Fu-An Wu , Jung-Ping Yang , Cheng Hung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
摘要翻译：器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。第一接触插塞在第一源极/漏极区域上电连接。第二接触插塞在第二源极/漏极区域之上并对齐。第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

26. 发明授权

US08437210B2 Asymmetric sense amplifier design 有权
标题翻译：非对称放大器设计
公开(公告)号：US08437210B2
公开(公告)日：2013-05-07
申请号：US13030722
申请日：2011-02-18
申请人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
发明人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/065
摘要： A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.
摘要翻译：电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。第二电容大于第一电容。

27. 发明授权

US08174911B2 Multi-power domain design 有权
标题翻译：多功能域设计
公开(公告)号：US08174911B2
公开(公告)日：2012-05-08
申请号：US12708923
申请日：2010-02-19
申请人： Hsu-Shun Chen , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Chung-Yi Wu , Chih-Chieh Chiu
发明人： Hsu-Shun Chen , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Chung-Yi Wu , Chih-Chieh Chiu
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C5/14
摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.
摘要翻译：在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

28. 发明申请

US20110188326A1 DUAL RAIL STATIC RANDOM ACCESS MEMORY 有权
标题翻译：双轨静态随机存取存储器
公开(公告)号：US20110188326A1
公开(公告)日：2011-08-04
申请号：US12700034
申请日：2010-02-04
申请人： Cheng Hung Lee , Hong-Chen Cheng , Chung-Ji Lu
发明人： Cheng Hung Lee , Hong-Chen Cheng , Chung-Ji Lu
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C7/00 , G11C8/08
摘要： A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control.
摘要翻译：静态随机存取存储器（SRAM）宏包括与第一电源电压不同的第一电源电压和第二电源电压。预充电控制连接到第二电源电压。预充电控制通过位线预充电耦合到位线。至少一个电平移位器接收电平移位器输入。电平移位器将具有比第二电源电压更接近于第一电源电压的电压电平的电平移位器输入转换为具有比第一电源电压更接近第二电源电压的电压电平的电平移位器输出。电平移位器输出被提供给预充电控制。

29. 发明授权

US07750375B2 Power line layout techniques for integrated circuits having modular cells 有权
标题翻译：具有模块化单元的集成电路的电源线布局技术
公开(公告)号：US07750375B2
公开(公告)日：2010-07-06
申请号：US11529925
申请日：2006-09-30
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： H01L27/10
CPC分类号： H01L27/0207 , H01L27/105
摘要： This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed to the first modular cell, also having the first metal layer, which contains at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first modular cell do not extend into the second modular cell, and all the power lines on the first metal layer serving the second modular cell do not extend into the first modular cell.
摘要翻译：本发明公开了一种具有多个模块单元的集成电路（IC）芯片，该芯片包括具有第一金属层的第一模块单元，该第一金属层包含彼此独立的至少两条电源线; 以及与第一模块单元并置的第二模块单元，其还具有第一金属层，该第一金属层包含彼此独立的至少两个电力线，其中用于第一模块单元的第一金属层上的所有电力线不延伸并且服务于第二模块的第一金属层上的所有电力线不延伸到第一模块单元中。

30. 发明授权

US07613057B2 Circuit and method for a sense amplifier 失效
标题翻译：一种读出放大器的电路和方法
公开(公告)号：US07613057B2
公开(公告)日：2009-11-03
申请号：US11732297
申请日：2007-04-03
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C5/025
摘要： A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided.
摘要翻译：一种电路和方法，用于为控制信号中的失真提供用于DRAM存储器的读出放大器，该读出放大器特别适用于将具有其他逻辑和存储器功能的DRAM存储器嵌入集成电路中。为具有级联耦合的晶体管对的读出放大器中的差分感测锁存器提供感测使能电路，每个晶体管接收单独的控制信号。单独的控制信号由具有延迟重叠的控制电路提供。当分离的控制信号之间存在延迟的重叠时，启用差分感测。 DRAM存储单元的阵列耦合到多个读出放大器。结合读出放大器的DRAM存储器可以与集成电路中的其它电路嵌入。提供了提供控制信号和用读出放大器布置DRAM存储器的方法。

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