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21. 发明授权

US06253304B1 Collation of interrupt control devices 有权
标题翻译：中断控制装置的整理
公开(公告)号：US06253304B1
公开(公告)日：2001-06-26
申请号：US09224821
申请日：1999-01-04
申请人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
发明人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
IPC分类号： G06F946
CPC分类号： G06F9/4812
摘要： A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.
摘要翻译：第一和第二局部中断控制器设置在单个集成电路上。第一和第二局部中断控制器被耦合以可分别地向第一和第二处理器提供至少一个中断请求信号。输入/输出（I / O）中断控制器也在集成电路上并被耦合以从至少一个输入/输出设备接收中断请求。集成电路上的通信电路耦合到输入/输出中断控制器和第一和第二本地中断控制器。通信电路提供第一局部中断控制器，第二局部中断控制器和输入/输出中断控制器之间的中断信息传输。

22. 发明授权

US06449713B1 Implementation of a conditional move instruction in an out-of-order processor 有权
标题翻译：在乱序处理器中实现条件移动指令
公开(公告)号：US06449713B1
公开(公告)日：2002-09-10
申请号：US09195121
申请日：1998-11-18
申请人： Joel Springer Emer , Bruce Edwards , Daniel Lawrence Leibholz , Edward J. McLellan , Derrick R. Meyer
发明人： Joel Springer Emer , Bruce Edwards , Daniel Lawrence Leibholz , Edward J. McLellan , Derrick R. Meyer
IPC分类号： G06F900
CPC分类号： G06F9/30094 , G06F9/30032 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3017
摘要： A technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The technique further involves replacing the conditional move instruction within the instruction stream with the generated multiple instructions. The generated multiple instructions are generated such that each of the generated multiple instructions executes using no more than two input ports of an execution unit. The generated multiple instructions include a first generated instruction that produces a condition result indicating whether a condition exists, and a second generated instruction that inputs the condition result as a portion of an operand which identifies a register of the out-of-order data processor. The second generated instruction performs a first move operation when the condition is determined to exist, and a second move operation when the condition is determined not to exist.
摘要翻译：用于处理乱序数据处理器中的条件移动指令的技术。该技术涉及检测指令流内的条件移动指令，并根据检测到的条件移动指令生成多条指令。该技术还包括用生成的多个指令来替换指令流内的条件移动指令。生成的多个指令被生成，使得每个生成的多个指令使用执行单元的不超过两个输入端口来执行。所生成的多个指令包括产生指示条件是否存在的条件结果的第一生成指令，以及输入条件结果作为识别无序数据处理器的寄存器的操作数的一部分的第二生成指令。当所述条件被确定为存在时，所述第二生成指令执行第一移动操作，以及当所述条件不存在时进行第二移动操作。

23. 发明授权

US06446215B1 Method and apparatus for controlling power management state transitions between devices connected via a clock forwarded interface 有权
标题翻译：用于控制经由时钟转发接口连接的设备之间的电源管理状态转换的方法和装置
公开(公告)号：US06446215B1
公开(公告)日：2002-09-03
申请号：US09378026
申请日：1999-08-20
申请人： Derrick R. Meyer , Scott A. White , Michael T. Clark , Philip E. Madrid
发明人： Derrick R. Meyer , Scott A. White , Michael T. Clark , Philip E. Madrid
IPC分类号： G06F126
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3253 , G06F13/405 , Y02D10/128 , Y02D10/151 , Y02D50/20
摘要： A method and apparatus for controlling power management state transitions between two devices, e.g., a processor and a bus bridge, that are connected through a clock forwarded interface bus in a computer system. The bus bridge is configured to coordinate disconnection of the processor from the interface. Particularly, the bus bridge may use a fist signal to indicate whether or not the processor is to be disconnected from the interface (e.g. a CONNECT signal) and the processor may use a second signal to indicate whether or not the processor is to be disconnected from the interface (e.g. a PROCREADY signal). The processor is disconnected from the interface responsive to both the first signal and the second signal indicating that the processor is to be disconnected. The signals may also be used to reconnect the processor to the interface.
摘要翻译：一种用于控制通过计算机系统中的时钟转发接口总线连接的两个设备（例如处理器和总线桥）之间的功率管理状态转换的方法和装置。总线桥被配置为协调处理器与接口的断开连接。特别地，总线桥可以使用第一信号来指示处理器是否与接口断开连接（例如，连接信号），并且处理器可以使用第二信号来指示处理器是否被断开接口（例如PROCREADY信号）。所述处理器响应于所述第一信号和所述第二信号指示所述处理器将被断开而与所述接口断开连接。信号也可用于将处理器重新连接到接口。

24. 发明授权

US06442677B1 Apparatus and method for superforwarding load operands in a microprocessor 有权
标题翻译：用于在微处理器中超载负载操作数的装置和方法
公开(公告)号：US06442677B1
公开(公告)日：2002-08-27
申请号：US09329497
申请日：1999-06-10
申请人： Derrick R. Meyer , Stephan G. Meier , Norbert Juffa
发明人： Derrick R. Meyer , Stephan G. Meier , Norbert Juffa
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/3826
摘要： An apparatus and method for superforwarding load operands in a microprocessor are provided. An execution unit in a microprocessor is configured to receive a load instruction and a subsequent instruction. If the load instruction corresponds to a simple load instruction, a destination operand of the load instruction can be superforwarded to a subsequent instruction if the subsequent instruction specifies a source operand that depends on the destination operand of the load instruction. The subsequent instruction is not required to wait until a load instruction executes or completes and can be scheduled and/or executed prior to or at the same time as the load instruction. Consequently, latencies associated with operand dependencies may be reduced.
摘要翻译：提供了一种用于在微处理器中超载负载操作数的装置和方法。微处理器中的执行单元被配置为接收加载指令和后续指令。如果加载指令对应于简单的加载指令，则如果后续指令指定依赖于加载指令的目的地操作数的源操作数，则加载指令的目标操作数可以被超前给后续指令。后续指令不需要等待加载指令执行或完成，并且可以在加载指令之前或同时进行调度和/或执行。因此，可以减少与操作数相关性相关联的延迟。

25. 发明授权

US06430639B1 Minimizing use of bus command code points to request the start and end of a lock 有权
标题翻译：最小化使用总线命令代码点来请求锁的开始和结束
公开(公告)号：US06430639B1
公开(公告)日：2002-08-06
申请号：US09339351
申请日：1999-06-23
申请人： Derrick R. Meyer , William K. Lewchuk
发明人： Derrick R. Meyer , William K. Lewchuk
IPC分类号： G06F1200
CPC分类号： G06F13/4004
摘要： A system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, such as a pair of uni-directional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency. point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited. from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system. The use of the locktoggle command may advantageously allow for the use of a single command code point, leaving other points available for other uses.
摘要翻译：一种用于使用切换命令来设置和释放锁的系统和方法，即锁定。在示例性计算机系统中，一个或多个处理器各自通过单独的高速连接耦合到总线桥，诸如具有各自的源同步时钟线的一对单向地址总线和具有伴随源的双向数据总线同步时钟线。 locktoggle命令用于将锁定请求和解锁请求从处理器传输到系统一致性。点，例如公交大桥。系统一致性点确认锁已经建立或释放。当锁活动时，其他处理器被禁止。至少访问锁启动的内存位置。因此，锁在系统一致性点处建立，这可有利地允许在非共享总线系统中锁定功能。使用locktoggle命令可以有利地允许使用单个命令代码点，使其他点可用于其他用途。

26. 发明授权

US6141734A Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol 失效
标题翻译：用于在写入无效协议的上下文中优化LDxL和STxC互锁指令的性能的方法和装置
公开(公告)号：US6141734A
公开(公告)日：2000-10-31
申请号：US17752
申请日：1998-02-03
申请人： Rahul Razdan , David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer , Daniel Lawrence Leibholz
发明人： Rahul Razdan , David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer , Daniel Lawrence Leibholz
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands.
摘要翻译：一种用于通过使用本地缓存来获取关于独占所有权的信息来实现加载锁定和存储条件指令原语的技术。有效位特别提供了正确执行加载锁定和存储条件指令的信息，而不需要锁定标志或每个单独锁定地址的本地锁定地址寄存器。锁定数据的完整性通过确保按顺序处理加载锁定和存储条件指令来实现，即内部代理可以将本地缓存中的块作为其处理的副作用来驱逐块，外部代理更新缓存存储器的上下文首先使用无效探测命令，并且只允许非推测性指令生成外部命令。

27. 发明授权

US6018798A Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle 失效
标题翻译：浮点单元使用中央窗口存储能够在单个时钟周期内执行多个指令的指令
公开(公告)号：US6018798A
公开(公告)日：2000-01-25
申请号：US993477
申请日：1997-12-18
申请人： David B. Witt , Derrick R. Meyer
发明人： David B. Witt , Derrick R. Meyer
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of translation units, a future file, a central window, a plurality of functional units, a result queue, and a plurality of physical registers. The floating point unit receives speculative instructions, decodes them, and then stores them in the central window. Speculative top of stack values are generated for each instruction during decoding. Top of stack relative operands are computed to physical registers using a register map. Register stack exchange operations are performed during decoding. Instructions are then stored in the central window, which selects the oldest stored instructions to be issued to each functional pipeline and issues them. Conversion units convert the instruction's operands to an internal format, and normalization units detect and normalize any denormal operands. Finally, the functional pipelines execute the instructions.
摘要翻译：公开了一种能够使用中央窗口和寄存器映射在单个时钟周期中执行多个指令的浮点单元。浮点单元包括：多个翻译单元，未来文件，中央窗口，多个功能单元，结果队列和多个物理寄存器。浮点单元接收推测指令，对它们进行解码，然后将其存储在中央窗口中。在解码过程中，每个指令产生堆栈值的推测顶点。堆栈顶部相对操作数使用寄存器映射计算到物理寄存器。在解码期间执行寄存器堆栈交换操作。然后将指令存储在中央窗口中，其中选择要发布到每个功能管道的最早存储的指令并发出它们。转换单位将指令的操作数转换为内部格式，归一化单元检测和归一化任何反常操作数。最后，功能管线执行指令。

28. 发明授权

US07146510B1 Use of a signal line to adjust width and/or frequency of a communication link during system operation 有权
标题翻译：在系统运行期间使用信号线来调整通信链路的宽度和/或频率
公开(公告)号：US07146510B1
公开(公告)日：2006-12-05
申请号：US10198637
申请日：2002-07-18
申请人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
发明人： Frank P. Helms , Derrick R. Meyer , Larry D. Hewitt , Dale E. Gulick , William A. Hughes , Scott E. Swanstrom
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.
摘要翻译：集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有集成电路进入复位状态。宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

29. 发明授权

US06668292B2 System and method for initiating a serial data transfer between two clock domains 有权
公开(公告)号：US06668292B2
公开(公告)日：2003-12-23
申请号：US10095019
申请日：2002-03-11
申请人： Derrick R. Meyer , Philip Enrique Madrid
发明人： Derrick R. Meyer , Philip Enrique Madrid
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received. The remainder of the serial data stream is received at appropriate intervals of the second clock rate.

30. 发明授权

US06549990B2 Store to load forwarding using a dependency link file 有权
标题翻译：存储以使用依赖关系链接文件加载转发
公开(公告)号：US06549990B2
公开(公告)日：2003-04-15
申请号：US09862687
申请日：2001-05-21
申请人： William Alexander Hughes , Derrick R. Meyer
发明人： William Alexander Hughes , Derrick R. Meyer
IPC分类号： G06F1200
CPC分类号： G06F9/3834 , G06F9/3826 , G06F9/3838
摘要： A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for the load. The entry stores a load identifier identifying the load and a store data identifier identifying a source of the store data. The dependency link file monitors results generated by execution units within the processor to detect the store data being provided. The dependency link file then causes the store data to be forwarded as the load data in response to detecting that the store data is provided. The latency from store data being provided to the load data being forwarded may thereby be minimized. Particularly, the load data may be forwarded without requiring that the load memory operation be scheduled.
摘要翻译：采用依赖关系链接文件的处理器。在检测到存储数据不可用的存储器的负载时，处理器在负载的依赖性链接文件内分配条目。条目存储标识负载的负载标识符和标识存储数据的源的存储数据标识符。依赖关系链接文件监视由处理器内的执行单元产生的结果，以检测正在提供的存储数据。响应于检测到提供存储数据，依赖关联链接文件使存储数据作为加载数据被转发。因此，提供给正在转发的负载数据的存储数据的延迟可以被最小化。特别地，可以转发负载数据，而不需要调度加载存储器操作。

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