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21. 发明授权

US06598206B2 Method and system of modifying integrated circuit power rails 有权
公开(公告)号：US06598206B2
公开(公告)日：2003-07-22
申请号：US09853115
申请日：2001-05-10
申请人： Laura R. Darden , Scott W. Gould , Patrick M. Ryan , Steven J. Urish
发明人： Laura R. Darden , Scott W. Gould , Patrick M. Ryan , Steven J. Urish
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.

22. 发明授权

US6134704A Integrated circuit macro apparatus 失效
标题翻译：集成电路宏器
公开(公告)号：US6134704A
公开(公告)日：2000-10-17
申请号：US54459
申请日：1998-04-03
申请人： John S. Adams , Grant L. Clarke, Jr. , Kenneth J. Goodnow , Scott W. Gould , Sebastian T. Ventrone
发明人： John S. Adams , Grant L. Clarke, Jr. , Kenneth J. Goodnow , Scott W. Gould , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus comprising a base macro, with fixed timing, surrounded by, and connected to, at least one selectable feature macro. The features of the apparatus may be selectively provided by connecting one or more of the selectable feature macros to the base macro.
摘要翻译：一种包括具有固定定时的基本宏的设备，由至少一个可选特征宏包围并连接到其上。可以通过将一个或多个可选特征宏连接到基本宏来选择性地提供装置的特征。

23. 发明授权

US5341310A Wiring layout design method and system for integrated circuits 失效
标题翻译：集成电路接线布局设计方法及系统
公开(公告)号：US5341310A
公开(公告)日：1994-08-23
申请号：US809681
申请日：1991-12-17
申请人： Scott W. Gould , Mark G. Marshall , Patrick E. Perry
发明人： Scott W. Gould , Mark G. Marshall , Patrick E. Perry
IPC分类号： G06F17/50 , H01L21/02 , G06F15/20
CPC分类号： G06F17/5077
摘要： A wiring layout design method and system providing efficient routing of wiring paths between multiple function blocks in an integrated circuit is disclosed. Associated with the function blocks are logic service terminals (LSTs) aligned on-grid relative to the global wiring layout. The technique utilizes a locator designating a desired contact point for each on-grid LST to be connected. The contact point designation is made without restriction relative to the predetermined grid pattern of the logic service terminals. Subsequent use of a conventional global wiring layout program to generate a layout of connections between LSTs, a reformatting program connects each wired logic service terminal to its desired contact point on the associated function block using the corresponding locator.
摘要翻译：公开了一种在集成电路中的多个功能块之间提供布线路径的有效布线的布线布局设计方法和系统。与功能块相关联的是逻辑服务终端（LST），它们在网格上相对于全局布线布局。该技术利用指定要连接的每个并网LST的期望接触点的定位器。接触点指定相对于逻辑服务终端的预定网格图形没有限制。随后使用传统的全局布线布局程序来生成LST之间的连接布局，重新格式化程序使用对应的定位器将每个有线逻辑服务终端连接到相关功能块上的所需接触点。

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