专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5822752A Method and apparatus for fast parallel determination of queue entries 失效
标题翻译：用于快速并行确定队列条目的方法和装置
公开(公告)号：US5822752A
公开(公告)日：1998-10-13
申请号：US680745
申请日：1996-07-15
申请人： Hoichi Cheong , Michael Kevin Ciraula , Hung Qui Le , John Stephen Muhich
发明人： Hoichi Cheong , Michael Kevin Ciraula , Hung Qui Le , John Stephen Muhich
IPC分类号： G06F12/02 , G06F7/78 , G06F12/00 , G06F13/00
CPC分类号： G06F7/785
摘要： The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.
摘要翻译：本发明涉及一种用于管理具有多个队列条目的随机顺序队列的电路，每个队列条目具有指示队列条目是否包含有效数据的相关联的有效位。在一个实施例中，电路包括用于响应于第一组有效位的接收有效信号的第一多个输入端，用于响应于第二组有效位而接收移位信号的第二多个输入端，以及用于提供选择耦合到队列的复用器的信号，所述选择信号响应于移位信号和有效信号。

22. 发明授权

US08418180B2 Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先级方法，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US08418180B2
公开(公告)日：2013-04-09
申请号：US12129876
申请日：2008-05-30
申请人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
发明人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

23. 发明申请

US20090063898A1 Processor Instruction Retry Recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US20090063898A1
公开(公告)日：2009-03-05
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/20
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

24. 发明授权

US07490226B2 Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor 失效
标题翻译：使用包括第一和第二位的矢量分量来调节微处理器中相关指令的移动的方法
公开(公告)号：US07490226B2
公开(公告)日：2009-02-10
申请号：US11054289
申请日：2005-02-09
申请人： Hung Qui Le , Dung Quoc Nguyen , Raymond Cheung Yeung
发明人： Hung Qui Le , Dung Quoc Nguyen , Raymond Cheung Yeung
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/3867
摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.
摘要翻译：提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器阶段。

25. 发明授权

US07467325B2 Processor instruction retry recovery 有权
标题翻译：处理器指令重试恢复
公开(公告)号：US07467325B2
公开(公告)日：2008-12-16
申请号：US11055258
申请日：2005-02-10
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

26. 发明申请

US20080288730A1 Transactional Memory System Which Employs Thread Assists Using Address History Tables 失效
标题翻译：使用地址历史表使用线程助手的事务内存系统
公开(公告)号：US20080288730A1
公开(公告)日：2008-11-20
申请号：US11928758
申请日：2007-10-30
申请人： Thomas J. Heller, JR. , Hung Qui Le
发明人： Thomas J. Heller, JR. , Hung Qui Le
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/0817
摘要： A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.
摘要翻译：计算系统使用专门的“集合关联事务表”和附加的“摘要事务表”来加速常见的事务性内存冲突情况的处理，以及使用地址历史表使用辅助线程的处理，并使用内存中的事务表处理内存事务通过支持应用程序不需要知道的并行处理多个执行线程。特殊说明可能标记交易的边界，并确定适用于交易的记忆位置。作为主数据存储存储器位置的一部分可直接寻址的“私有交易”（PTRAN）标签使得能够快速检测与所述计算系统的另一个线程上并发执行的其他事务的潜在冲突。标记表示（或不）内存中的数据条目是系统中当前处于活动状态的未提交事务的推测性存储器状态的一部分。

27. 发明申请

US20080222395A1 System and Method for Predictive Early Allocation of Stores in a Microprocessor 失效
标题翻译：微处理器中商店预测性早期分配的系统和方法
公开(公告)号：US20080222395A1
公开(公告)日：2008-09-11
申请号：US11683843
申请日：2007-03-08
申请人： Hung Qui Le , Dung Quoc Nguyen
发明人： Hung Qui Le , Dung Quoc Nguyen
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3857 , G06F9/3859
摘要： A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the instruction dispatch unit loads the interruptible instruction's instruction tag (IITAG) into an interruptible instruction tag register. A load store unit loads subsequent instruction information (instruction tag and store data) along with the interruptible instruction tag in a store data queue entry. Comparison logic receives a completing instruction tag from completion logic, and compares the completing instruction tag with the interruptible instruction tags included in the store data queue entries. In turn, deallocation logic deallocates those store data queue entries that include an interruptible instruction tag that matches the completing instruction tag.
摘要翻译：提出了一种用于在微处理器中预先提前存储分配的系统和方法。在指令调度期间，指令调度单元从指令高速缓存（Icache）检索指令。当检索到的指令是可中断指令时，指令调度单元将可中断指令的指令标记（IITAG）加载到可中断指令标记寄存器中。加载存储单元将后续指令信息（指令标签和存储数据）与可中断指令标签一起存储在存储数据队列条目中。比较逻辑从完成逻辑接收完成指令标记，并将完成指令标签与包含在存储数据队列条目中的可中断指令标签进行比较。反过来，解配分配逻辑会释放那些包含与完成指令标记匹配的可中断指令标签的存储数据队列条目。

28. 发明授权

US07051177B2 Method for measuring memory latency in a hierarchical memory system 失效
标题翻译：用于测量分层存储器系统中的存储器延迟的方法
公开(公告)号：US07051177B2
公开(公告)日：2006-05-23
申请号：US10210359
申请日：2002-07-31
申请人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
发明人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F12/00 , G06F12/14 , G06F12/16 , G06F13/00 , G06F13/28
CPC分类号： G06F11/3466 , G06F11/3419 , G06F12/0897 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.
摘要翻译：公开了一种用于确定分层存储器系统内特定级别的存储器的等待时间的方法。分配性能监视计数器来计数负载数（负载计数器）和计数周期数（循环计数器）。该方法开始于处理器确定要选择用于测量的负载。响应于该确定，周期计数器值被存储在倒带寄存器中。处理器发出负载并开始计数周期。响应于负载完成，确定负载的存储器级别。如果从期望的存储器级别执行负载，则负载计数器递增。否则，循环计数器将重绕到其先前的值。

29. 发明授权

US07047398B2 Analyzing instruction completion delays in a processor 失效
标题翻译：分析处理器中的指令完成延迟
公开(公告)号：US07047398B2
公开(公告)日：2006-05-16
申请号：US10210358
申请日：2002-07-31
申请人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Michitaka Okuno , Masahiro Tokoro
发明人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3865 , G06F11/3466 , G06F2201/88
摘要： A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.
摘要翻译：一种用于识别计算机处理器中的一组指令的指令完成延迟的方法和系统。指令组中的每个指令都有一个状态指示器，用于标识阻止该指令完成执行的内容。完成延迟的示例是缓存未命中，数据依赖性或简单地计算机处理器中的执行单元处理指令所需的时间。每个指令执行完毕后，相关状态指示灯将被清除，表示该指令不再等待执行。执行的最后一条指令是保持整个组的完成的指令，因此将最后指令的完成延迟的原因记录为整个组的完成延迟的原因。

30. 发明授权

US06910120B2 Speculative counting of performance events with rewind counter 失效
标题翻译：用倒带计数器推测性能事件计数
公开(公告)号：US06910120B2
公开(公告)日：2005-06-21
申请号：US10210357
申请日：2002-07-31
申请人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
发明人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F9/00 , G06F9/38 , G06F11/34
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored in a rewind register. The performance monitor counter is incremented in response to predetermined events. If the microprocessor determines the speculative execution was incorrect, the value of the rewind register is loaded into the counter, restoring correct value for the counter.
摘要翻译：公开了一种用于在推测性计算机微处理器内在性能监视计数器中维持正确值的电路和方法。响应于确定微处理器内的推测执行开始，性能监视计数器的值被存储在倒带寄存器中。性能监视计数器响应于预定事件递增。如果微处理器确定推测执行不正确，倒带寄存器的值将被加载到计数器中，恢复计数器的正确值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式