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1. 发明授权

US5822752A Method and apparatus for fast parallel determination of queue entries 失效
标题翻译：用于快速并行确定队列条目的方法和装置
公开(公告)号：US5822752A
公开(公告)日：1998-10-13
申请号：US680745
申请日：1996-07-15
申请人： Hoichi Cheong , Michael Kevin Ciraula , Hung Qui Le , John Stephen Muhich
发明人： Hoichi Cheong , Michael Kevin Ciraula , Hung Qui Le , John Stephen Muhich
IPC分类号： G06F12/02 , G06F7/78 , G06F12/00 , G06F13/00
CPC分类号： G06F7/785
摘要： The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.
摘要翻译：本发明涉及一种用于管理具有多个队列条目的随机顺序队列的电路，每个队列条目具有指示队列条目是否包含有效数据的相关联的有效位。在一个实施例中，电路包括用于响应于第一组有效位的接收有效信号的第一多个输入端，用于响应于第二组有效位而接收移位信号的第二多个输入端，以及用于提供选择耦合到队列的复用器的信号，所述选择信号响应于移位信号和有效信号。

2. 发明授权

US5870582A Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched 失效
标题翻译：在发出指令前完成不可中断指令的方法和装置
公开(公告)号：US5870582A
公开(公告)日：1999-02-09
申请号：US829671
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3863
摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.
摘要翻译：在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。处理器资源被窥探以获得标记指令的执行结果。响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。重命名缓冲器可以包括历史缓冲器。此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。因此，在这样的组中可能存在许多不可中断的指令。这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

3. 发明授权

US5860014A Method and apparatus for improved recovery of processor state using history buffer 失效
标题翻译：使用历史缓冲区来改善处理器状态恢复的方法和装置
公开(公告)号：US5860014A
公开(公告)日：1999-01-12
申请号：US729307
申请日：1996-10-15
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3861
摘要： A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.
摘要翻译：一种用于维护使用寄存器处理指令的处理器的寄存器的内容的方法和装置。条目存储在缓冲器中，用于通过可中断指令中断来恢复寄存器内容。条目包括用于减少为恢复选择的条目数量的信息。响应于中断和信息来选择一组缓冲器条目用于恢复寄存器内容。该集合仅包括为了响应于中断而恢复内容所必需的条目，使得处理器寄存器的内容可以在单个处理器周期中被恢复，即使对于第一个寄存器和多个条目存储了多个条目存储在第二个寄存器中。

4. 发明授权

US6098167A Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution 失效
标题翻译：支持无序执行的处理器的快速统一中断恢复和分支恢复的装置和方法
公开(公告)号：US6098167A
公开(公告)日：2000-08-01
申请号：US829667
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863
摘要： In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.
摘要翻译：在维护处理器的状态时，在架构寄存器表中给出分派指令的识别标签和相关联的条目。如果调度指令的识别标签比存储在条目中的先前指令标识标签更新，则将调度指令的识别标签写入架构寄存器表中的条目。

5. 发明授权

US5913048A Dispatching instructions in a processor supporting out-of-order execution 失效
标题翻译：支持无序执行的处理器中的调度指令
公开(公告)号：US5913048A
公开(公告)日：1999-06-15
申请号：US829663
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of assigning an identification tag to an instruction, and dispatching the instruction, the identification tag and source information to an execution queue.
摘要翻译：本发明涉及一种在处理器中发出指令的方法。在本发明的一个版本中，该方法包括以下步骤：向指令分配识别标签，并将指令，识别标签和源信息分派到执行队列。

6. 发明授权

US5887161A Issuing instructions in a processor supporting out-of-order execution 失效
标题翻译：在支持无序执行的处理器中发出指令
公开(公告)号：US5887161A
公开(公告)日：1999-03-23
申请号：US829662
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.
摘要翻译：本发明涉及一种在处理器中发出指令的方法。在本发明的一个版本中，该方法包括以下步骤：将指令和源信息发送到队列，确定源信息的有效性，以及响应源信息有效性发出执行指令。

7. 发明授权

US5870612A Method and apparatus for condensed history buffer 失效
标题翻译：精简历史缓冲区的方法和装置
公开(公告)号：US5870612A
公开(公告)日：1999-02-09
申请号：US729309
申请日：1996-10-15
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/462 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： The invention includes a method and apparatus for maintaining content of predefined registers of a processor which uses the registers for executing instructions, including an interruptible instruction. According to the invention, instructions are dispatched, including instructions ("targeting instructions") which target registers for holding register content, and an interruptible instruction. The content of a register is altered in response to executing a targeting instruction. An entry of register content is stored only for selected ones of the dispatched targeting instructions.
摘要翻译：本发明包括一种用于维护处理器的预定义寄存器的内容的方法和装置，其使用该寄存器来执行包括可中断指令的指令。根据本发明，调度指令，包括目标用于保持寄存器内容的寄存器的指令（“目标指令”）和可中断指令。响应于执行目标指令而改变寄存器的内容。注册内容的条目仅存储于所选派生的定位指令。

8. 发明授权

US5805906A Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions 失效
标题翻译：使用多个用于处理指令的寄存器在数据处理系统中向寄存器写入信息的方法和装置
公开(公告)号：US5805906A
公开(公告)日：1998-09-08
申请号：US729308
申请日：1996-10-15
申请人： Hoichi Cheong , Hung Qui Le , Paul Joseph Jordan
发明人： Hoichi Cheong , Hung Qui Le , Paul Joseph Jordan
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3855 , G06F9/30141 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to processor registers, information ("results") resulting from and associated with executing instructions. Certain of the results are stored for restoring to the registers. In response to an interruption at least one of the ports is accessed for restoring stored results to the registers. Accesses to the ports are arbitrated in response to comparing writeback and restoration results. A result includes identification of the instruction the result is associated with (a "TID"), and a register that is targeted by the result (a "TR"). The comparing includes comparing TID's and TR's for the results.
摘要翻译：在使用多个用于处理指令的寄存器的数据处理系统中，用于将信息写入寄存器的方法和装置。访问端口以写回处理器寄存器，由执行指令产生并与执行指令相关联的信息（“结果”）。某些结果存储用于恢复到寄存器。响应于中断，访问至少一个端口以将存储的结果恢复到寄存器。响应于回写和恢复结果的比较，对端口的访问进行仲裁。结果包括与结果相关联的指令的识别（“TID”）和由结果（“TR”）定向的寄存器。比较包括比较TID和TR的结果。

9. 发明授权

US6061777A Apparatus and method for reducing the number of rename registers required in the operation of a processor 失效
标题翻译：用于减少处理器操作所需的重命名寄存器的数量的装置和方法
公开(公告)号：US6061777A
公开(公告)日：2000-05-09
申请号：US959646
申请日：1997-10-28
申请人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le , Soummya Mallick
发明人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le , Soummya Mallick
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863 , G06F9/384
摘要： One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.
摘要翻译：本发明的一个方面涉及一种用于操作处理器的方法。在本发明的一个版本中，该方法包括发送指令的步骤; 确定由发送的指令所针对的架构寄存器的目前架构化的RMAP条目; 选择与包含调度指令的操作数的物理寄存器相关联的RMAP条目; 更新所选RMAP条目中的使用指示符; 确定发送的指令是否可中断; 以及如果所分派的指令是不间断的，则更新当前架构的RMAP条目中的架构指示符和历史指示符。

10. 发明授权

US5983341A Data processing system and method for extending the time for execution of an instruction 失效
标题翻译：用于延长执行指令的时间的数据处理系统和方法
公开(公告)号：US5983341A
公开(公告)日：1999-11-09
申请号：US840921
申请日：1997-04-25
申请人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le
发明人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le
IPC分类号： G06F9/38 , G06F9/06 , G06F9/22
CPC分类号： G06F9/3836 , G06F9/3855
摘要： A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.
摘要翻译：数据处理系统指示由于缓存未命中或由于非高速缓存未命中延迟而导致指令没有可用数据。当指令不能访问可用数据并且高速缓存未命中时，不发出取决于发出的指令的指令。然而，如果由于非高速缓存未命中延迟而导致负载执行被延迟，那么取决于所发出的指令的指令也是在下一个定时周期中预期成功的加载指令执行的情况下发出的。通过使用这种发布机制，随着执行单元更好地利用其管道，数据处理系统的效率得到提高。

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