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21. 发明授权

US5220533A Method and apparatus for preventing overerasure in a flash cell 失效
标题翻译：用于防止闪存中的超频的方法和装置
公开(公告)号：US5220533A
公开(公告)日：1993-06-15
申请号：US788607
申请日：1991-11-06
申请人： John E. Turner
发明人： John E. Turner
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/14 , G11C16/16 , H03K19/173 , H03K19/177
CPC分类号： G11C16/3477 , G11C16/14 , G11C16/16
摘要： A method and apparatus for erasing Flash EPROM cells that avoids overerasure is provided. A high-impedance device is placed between the drain of the cell and the high-voltage supply used to erase the cell. As soon as the cell enters the onset of depletion and begins to conduct, most of the high voltage is dropped across the high-impedance device, leaving insufficient potential across the cell for Fowler-Nordheim tunneling to continue. The erase process is thus self-limiting. The process can be used on a chain or array of EPROM cells, with erasure stopping when any one of the cells conducts. Bias differences between erase and read modes assure that the cell that first goes into depletion is not in depletion in normal operation.

22. 发明授权

US4896296A Programmable logic device configurable input/output cell 失效
标题翻译：可编程逻辑器件可配置输入/输出单元
公开(公告)号：US4896296A
公开(公告)日：1990-01-23
申请号：US288945
申请日：1988-12-23
申请人： John E. Turner , David L. Rutledge , Roy D. Darling
发明人： John E. Turner , David L. Rutledge , Roy D. Darling
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： H03K19/17772 , G01R31/318516 , H03K19/17704 , H03K19/17744 , H03K19/1776 , H03K19/1778
摘要： An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.
摘要翻译：公开了一种系统可编程逻辑器件，其可以在安装在用户系统中时配置或重新配置。所公开的设备使用诸如浮动栅极晶体管之类的非易失性存储单元作为可编程元件，因此该器件在掉电状态期间实际上无限期地保留特定的编程逻辑配置。该设备可在正常状态和几种工作状态下操作，以重新配置设备。器件状态由内部状态机控制，内部状态机执行几个状态方程，其变量是驱动两个专用引脚的逻辑电平和当前器件状态。一个器件引脚接收串行输入数据，它加载一个移位寄存器锁存器。锁存器的内容用于选择要编程的单元格的特定行以及所选单元格要被编程的逻辑电平。设备正常输入和输出在使用状态下与设备隔离，以便在用电状态期间用户系统不会影响设备的运行。包括电压倍增器电路以产生将来自器件电源电压的用作器件存储单元的浮栅晶体管编程所需的高电压电平，从而进一步节省所需数量的器件引脚。通过编程特定存储器单元，用户可以在用电状态期间将设备输出的状态选择为当前数据锁存状态或三态条件。

23. 发明授权

US4879688A In-system programmable logic device 失效
标题翻译：在系统可编程逻辑器件
公开(公告)号：US4879688A
公开(公告)日：1989-11-07
申请号：US862815
申请日：1986-05-13
申请人： John E. Turner , David L. Rutledge , Roy D. Darling
发明人： John E. Turner , David L. Rutledge , Roy D. Darling
IPC分类号： G06F7/00 , G01R31/3185 , G11C16/04 , G11C17/00 , H03K19/177
CPC分类号： G01R31/318516 , H03K19/17704 , H03K19/17748 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.
摘要翻译：公开了一种系统可编程逻辑器件，其可以在安装在用户系统中时配置或重新配置。所公开的设备使用诸如浮动栅极晶体管之类的非易失性存储单元作为可编程元件，因此该器件在掉电状态期间实际上无限期地保留特定的编程逻辑配置。该设备可在正常状态和几种工作状态下操作，以重新配置设备。器件状态由内部状态机控制，内部状态机执行几个状态方程，其变量是驱动两个专用引脚的逻辑电平和当前器件状态。一个器件引脚接收串行输入数据，它加载一个移位寄存器锁存器。锁存器的内容用于选择要编程的单元格的特定行以及所选单元格要被编程的逻辑电平。设备正常输入和输出在使用状态下与设备隔离，以便在用电状态期间用户系统不会影响设备的运行。包括电压倍增器电路以产生将来自器件电源电压的用作器件存储单元的浮栅晶体管编程所需的高电压电平，从而进一步节省所需数量的器件引脚。通过编程特定存储器单元，用户可以在用电状态期间将设备输出的状态选择为当前数据锁存状态或三态条件。

24. 发明授权

US4855954A In-system programmable logic device with four dedicated terminals 失效
标题翻译：具有四个专用端子的系统内可编程逻辑器件
公开(公告)号：US4855954A
公开(公告)日：1989-08-08
申请号：US262493
申请日：1988-10-25
申请人： John E. Turner , David L. Rutledge , Roy D. Darling
发明人： John E. Turner , David L. Rutledge , Roy D. Darling
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： H03K19/17772 , G01R31/318516 , H03K19/17704 , H03K19/1776 , H03K19/1778
摘要： An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.
摘要翻译：公开了一种系统可编程逻辑器件，其可以在安装在用户系统中时配置或重新配置。所公开的装置使用诸如浮动栅极晶体管之类的非易失性存储单元作为可编程元件，因此该器件在掉电状态期间实际上无限期地保留特定的编程逻辑配置。该设备可在正常状态和几种工作状态下操作，以重新配置设备。器件状态由内部状态机控制，内部状态机执行几个状态方程，其变量是驱动两个专用引脚的逻辑电平和当前器件状态。一个器件引脚接收串行输入数据，它加载一个移位寄存器锁存器。锁存器的内容用于选择要编程的单元格的特定行以及所选单元格要被编程的逻辑电平。设备正常输入和输出在使用状态下与设备隔离，以便在用电状态期间用户系统不会影响设备的运行。包括电压倍增器电路以产生将来自器件电源电压的用作器件存储单元的浮栅晶体管编程所需的高电压电平，从而进一步节省所需数量的器件引脚。通过编程特定存储器单元，用户可以在用电状态期间将设备输出的状态选择为当前数据锁存状态或三态条件。

25. 发明授权

US06828620B2 Nonvolatile memory cell with low doping region 失效
标题翻译：具有低掺杂区域的非易失性存储单元
公开(公告)号：US06828620B2
公开(公告)日：2004-12-07
申请号：US10436644
申请日：2003-05-12
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H01L29788
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
摘要翻译：制造非易失性器件的技术包括形成低掺杂区域以有助于还原衬底热电子。非易失性器件可以是诸如闪存，EEPROM或EPROM存储器单元的浮动栅极器件。低掺杂区域的掺杂浓度低于衬底的掺杂浓度。通过减少衬底热电子，这提高了非易失性器件的可靠性和寿命。

26. 发明授权

US06724222B2 Programmable logic with lower internal voltage circuitry 失效
标题翻译：具有较低内部电压电路的可编程逻辑
公开(公告)号：US06724222B2
公开(公告)日：2004-04-20
申请号：US10366814
申请日：2003-02-13
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K19175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique and circuitry interfaces a programmable logic integrated circuit compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, an on-chip voltage less than the external supply level of the programmable logic integrated circuit is provided to a core portion of a programmable logic integrated circuit by way of a conversion transistor. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. Externally, the programmable logic integrated circuit will interface with an external supply voltage level. The input and output signals to and from the programmable logic integrated circuit will be compatible with the external supply level.
摘要翻译：技术和电路将与一个电压电平兼容的可编程逻辑集成电路与不同电压电平兼容的其他集成电路接口。特别地，通过转换晶体管将可编程逻辑集成电路的小于外部电源电平的片上电压提供给可编程逻辑集成电路的核心部分。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。在外部，可编程逻辑集成电路将与外部电源电压接口。来自可编程逻辑集成电路的输入和输出信号将与外部电源电平兼容。

27. 发明授权

US06583646B1 Overvoltage-tolerant interface for integrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06583646B1
公开(公告)日：2003-06-24
申请号：US09860028
申请日：2001-05-16
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad which is above a supply voltage for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator for preventing leakage current paths.
摘要翻译：一个输入/输出驱动器，用于直接与焊盘上的电压进行接口，该电压高于输入/输出驱动器的电源电压。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止漏电流路径的阱偏置发生器。

28. 发明授权

US06563343B1 Circuitry for a low internal voltage 有权
标题翻译：电路内部电压低
公开(公告)号：US06563343B1
公开(公告)日：2003-05-13
申请号：US10136944
申请日：2002-04-30
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.
摘要翻译：一种技术通过转换晶体管向集成电路的核心部分提供片上电压。片上电压可能是内部电压降低，小于集成电路的VCC。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。通过为内核提供降低的电压，集成电路可以与与不同电压电平兼容的其他集成电路接口。

29. 发明授权

US06414518B1 Circuitry for a low internal voltage integrated circuit 有权
标题翻译：用于集成电路的结构，以提供片上电压
公开(公告)号：US06414518B1
公开(公告)日：2002-07-02
申请号：US09449166
申请日：1999-11-24
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K1900
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.
摘要翻译：一种技术通过转换晶体管向集成电路的核心部分提供片上电压。片上电压可能是内部电压降低，小于集成电路的VCC。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。通过为内核提供降低的电压，集成电路可以与与不同电压电平兼容的其他集成电路接口。

30. 发明授权

US06342794B1 Interface for low-voltage semiconductor devices 有权
标题翻译：低压半导体器件接口
公开(公告)号：US06342794B1
公开(公告)日：2002-01-29
申请号：US09621939
申请日：2000-07-24
申请人： John E. Turner , Rakesh H. Patel
发明人： John E. Turner , Rakesh H. Patel
IPC分类号： H03K190185
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique and circuitry to interface an integrated circuit to other integrated circuits in a mixed-voltage mode environment. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage level. The input and output signals to and from the integrated circuit will be compatible with the external supply level. Specifically, a level shifter (1317) or similar conversion circuit is used to convert voltages compatible with the internal supply level to be compatible with the external supply level.
摘要翻译：将集成电路与混合电压模式环境中的其他集成电路接口的技术和电路。特别地，使用与内部电源电压相兼容的技术来制造集成电路。在外部，集成电路将与外部电源电压接口，高于内部电源电压电平。来往于集成电路的输入和输出信号将与外部电源电平兼容。具体地说，电平移位器（1317）或类似的转换电路用于将与内部电源电平兼容的电压转换为与外部电源电平兼容。

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