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21. 发明申请

US20070048993A1 Semiconductor product and method for forming a semiconductor product 有权
标题翻译：用于形成半导体产品的半导体产品和方法
公开(公告)号：US20070048993A1
公开(公告)日：2007-03-01
申请号：US11217122
申请日：2005-08-31
申请人： Josef Willer , Patrick Haibach , Christoph Kleint , Nicolas Nagel
发明人： Josef Willer , Patrick Haibach , Christoph Kleint , Nicolas Nagel
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.
摘要翻译：半导体产品包括具有基板表面的基板。多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。在字线之间提供多个导电接触结构。该产品还包括多个填充结构。每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。两个相应的接触结构在第一方向上彼此间隔一定距离。在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

22. 发明授权

US07678654B2 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US07678654B2
公开(公告)日：2010-03-16
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
IPC分类号： H01L21/8247 , H01L29/792
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

23. 发明申请

US20080002466A1 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US20080002466A1
公开(公告)日：2008-01-03
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Muller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Muller , Hocine Boubekeur
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

24. 发明申请

US20080296778A1 Interconnection Structure and Integrated Circuit 审中-公开
标题翻译：互连结构与集成电路
公开(公告)号：US20080296778A1
公开(公告)日：2008-12-04
申请号：US11755483
申请日：2007-05-30
申请人： Martin Roessiger , Christoph Kleint
发明人： Martin Roessiger , Christoph Kleint
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L23/485 , H01L21/76837 , H01L21/76885 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit and an interconnection structure includes forming a conductive portion along a first direction and conductive lines along a second direction.
摘要翻译：集成电路和互连结构的制造方法包括沿着第一方向形成导电部分，沿着第二方向形成导电线。

25. 发明授权

US08009477B2 Integrated circuit and method of forming an integrated circuit 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US08009477B2
公开(公告)日：2011-08-30
申请号：US12182714
申请日：2008-07-30
申请人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
发明人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
IPC分类号： G11C11/40 , H01L27/088 , H01L29/78 , H01L21/4763
CPC分类号： G11C5/063 , H01L21/76804 , H01L21/76807 , H01L21/76813
摘要： An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.
摘要翻译：集成电路和形成集成电路的方法。一个实施例包括形成在载体的表面上方的导线。在垂直于载体表面的方向上的导线的侧壁的斜面显示出不连续性，并且导电线的上部的宽度大于下部的对应宽度。

26. 发明申请

US20100027311A1 INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20100027311A1
公开(公告)日：2010-02-04
申请号：US12182714
申请日：2008-07-30
申请人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
发明人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
IPC分类号： H01L21/768 , G11C5/06
CPC分类号： G11C5/063 , H01L21/76804 , H01L21/76807 , H01L21/76813
摘要： An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.
摘要翻译：集成电路和形成集成电路的方法。一个实施例包括形成在载体的表面上方的导线。在垂直于载体表面的方向上的导线的侧壁的斜面显示出不连续性，并且导电线的上部的宽度大于下部的对应宽度。

27. 发明申请

US20060267078A1 CHARGE-TRAPPING MEMORY DEVICE 失效
标题翻译：充电跟踪存储器件
公开(公告)号：US20060267078A1
公开(公告)日：2006-11-30
申请号：US11141254
申请日：2005-05-31
申请人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
发明人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.
摘要翻译：氧化区域布置在半导体材料的衬底和氮化物衬垫之间，其覆盖存储单元阵列的字线堆叠和衬底的中间区域，并且被提供以将氮化物衬垫与衬底和存储器层序列分离的电介质材料，用于电荷捕获。氮化物衬垫在形成用于外围区域的侧壁间隔物中用作蚀刻停止层，以产生寻址电路的晶体管的源极/漏极结。

28. 发明授权

US07462038B2 Interconnection structure and method of manufacturing the same 有权
标题翻译：互连结构及制造方法
公开(公告)号：US07462038B2
公开(公告)日：2008-12-09
申请号：US11676622
申请日：2007-02-20
申请人： Roman Knoefler , Christoph Kleint , Steffen Meyer , Nicolas Nagel
发明人： Roman Knoefler , Christoph Kleint , Steffen Meyer , Nicolas Nagel
IPC分类号： H01R12/00
CPC分类号： H01R13/22
摘要： An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.
摘要翻译：互连结构包括具有均匀间隔的接触的两个交错的接触排。每个接触排沿第一方向延伸。互连结构还包括沿着与第一方向相交的第二方向延伸的导电线。互连结构还包括中间触点，其中每个中间触点与触点之一和导线中的一个接触。

29. 发明申请

US20080200046A1 INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20080200046A1
公开(公告)日：2008-08-21
申请号：US11676622
申请日：2007-02-20
申请人： Roman Knoefler , Christoph Kleint , Steffen Meyer , Nicolas Nagel
发明人： Roman Knoefler , Christoph Kleint , Steffen Meyer , Nicolas Nagel
IPC分类号： H01R12/00
CPC分类号： H01R13/22
摘要： An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.
摘要翻译：互连结构包括具有均匀间隔的接触的两个交错的接触排。每个接触排沿第一方向延伸。互连结构还包括沿着与第一方向相交的第二方向延伸的导电线。互连结构还包括中间触点，其中每个中间触点与触点之一和导线中的一个接触。

30. 发明申请

US20070048951A1 Method for production of semiconductor memory devices 审中-公开
标题翻译：半导体存储器件的制造方法
公开(公告)号：US20070048951A1
公开(公告)日：2007-03-01
申请号：US11216526
申请日：2005-08-31
申请人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
发明人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.
摘要翻译：介质光栅形成在字线堆叠之间。间隔件被施加到字线堆叠和介质光栅的侧壁。在间隔物之间的开口中，硅在源/漏区的上表面上外延生长，其被注入自对准到字线堆叠。在生长的硅上形成硅化物，并且施加和构造金属层以形成局部互连，其将源极/漏极区域连接到高位线。

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