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21. 发明申请

US20100208504A1 Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 有权
标题翻译：识别磁包存储器存储设备中的数据位置，包括这种设备的存储器系统以及控制这些设备的方法
公开(公告)号：US20100208504A1
公开(公告)日：2010-08-19
申请号：US12658859
申请日：2010-02-16
申请人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
发明人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
IPC分类号： G11C19/00 , G11C7/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C19/0841
摘要： In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.
摘要翻译：在存储器装置和用于控制存储器件的方法中，存储器件包括将结构存储在磁性结构的多个域中的磁性结构。读取单元通过向磁性结构施加读取电流来从磁性结构的多个域中的至少一个域读取信息。位置检测器单元将来自读取单元的读取电流读取的信息与磁性结构的多个域的多个域进行比较，以识别多个域的选定域处的预期信息模式的存在。

22. 发明授权

US07009257B2 Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby 有权
公开(公告)号：US07009257B2
公开(公告)日：2006-03-07
申请号：US10741751
申请日：2003-12-19
申请人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
发明人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
IPC分类号： H01L29/72
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823475
摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

23. 发明授权

US06576963B2 Semiconductor device having transistor 失效
标题翻译：具有晶体管的半导体器件
公开(公告)号：US06576963B2
公开(公告)日：2003-06-10
申请号：US09992069
申请日：2001-11-14
申请人： Beom-jun Jin , Byeong-yun Nam , Young-pil Kim
发明人： Beom-jun Jin , Byeong-yun Nam , Young-pil Kim
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/823475 , H01L29/6653 , Y10S257/90
摘要： A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.
摘要翻译：提供了一种使用仅使用蚀刻掩模层在半导体衬底中暴露源/漏区的自对准接触孔的方法。在该方法中，牺牲隔离物由对单元区域中的栅电极的侧壁处的蚀刻掩模层具有优良蚀刻选择性的材料形成。此外，层间介电层由对蚀刻掩模层具有优异蚀刻选择性的材料形成。当形成自对准的接触孔时，去除牺牲隔离物。电介质间隔物由具有低介电常数的材料形成，而不考虑其对层间电介质层的蚀刻选择性。因此，可以防止具有晶体管的半导体器件的操作速度的降低。

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