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21. 发明授权

US07376815B2 Methods and apparatus to insure correct predecode 有权
标题翻译：确保正确预解码的方法和装置
公开(公告)号：US07376815B2
公开(公告)日：2008-05-20
申请号：US11066957
申请日：2005-02-25
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F8/447 , G06F9/382
摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.
摘要翻译：公开了用于确保指令串的同步预解码的技术。指令串包含来自可变长度指令集和嵌入数据的指令。一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

22. 发明授权

US08438371B2 Link stack repair of erroneous speculative update 有权
标题翻译：链接堆栈修复错误的推测更新
公开(公告)号：US08438371B2
公开(公告)日：2013-05-07
申请号：US13108227
申请日：2011-05-16
申请人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
发明人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

23. 发明授权

US08082428B2 Methods and system for resolving simultaneous predicted branch instructions 有权
标题翻译：解决同步预测分支指令的方法和系统
公开(公告)号：US08082428B2
公开(公告)日：2011-12-20
申请号：US12569365
申请日：2009-09-29
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
摘要： A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
摘要翻译：公开了一种在预测分支指令验证之前解决同步分支预测的方法。该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。该方法还包括选择一个校正状态。如果预测的分支指令之一被错误预测，则所选择的校正状态用于指示未来的指令提取。

24. 发明申请

US20090119485A1 Predecode Repair Cache For Instructions That Cross An Instruction Cache Line 有权
标题翻译：预编码修复缓存用于交叉指令缓存行的指令
公开(公告)号：US20090119485A1
公开(公告)日：2009-05-07
申请号：US11934108
申请日：2007-11-02
申请人： Rodney Wayne Smith , Brian Michael Stempel , David John Mandzak , James Norris Dieffenderfer
发明人： Rodney Wayne Smith , Brian Michael Stempel , David John Mandzak , James Norris Dieffenderfer
IPC分类号： G06F9/312
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length and a second length, the second length longer than the first length. A predecoder is operable to predecode instructions fetched from the instruction cache that have invalid predecode information to form repaired predecode information. A predecode repair cache is operable to store the repaired predecode information associated with instructions of the second length that span across two cache lines in the instruction cache. Methods for filling the predecode repair cache and for executing an instruction that spans across two cache lines are also described.
摘要翻译：在能够获取和执行具有至少两个可能在程序中混合的长度的指令的可变长度指令的处理器中描述了一个预解码修复高速缓存。指令高速缓存用于存储指令高速缓存行指令，该指令具有至少第一长度和第二长度，第二长度长于第一长度。预解码器可用于对具有无效预解码信息的指令高速缓存取出的指令进行预解码，以形成修复的预解码信息。预解码修复高速缓存可操作用于存储与跨越指令高速缓存中的两个高速缓存行的第二长度的指令相关联的修复的预解码信息。还描述了用于填充预解码修复高速缓存和用于执行跨越两个高速缓存行的指令的方法。

25. 发明申请

US20080109644A1 System and method for using a working global history register 有权
标题翻译：使用工作全球历史记录寄存器的系统和方法
公开(公告)号：US20080109644A1
公开(公告)日：2008-05-08
申请号：US11556244
申请日：2006-11-03
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3804 , G06F9/3806 , G06F9/3861
摘要： A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register, wherein the first register. The method further loads the branch history information into the second register during the second pipeline stage.
摘要翻译：公开了处理分支历史信息的方法。该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。该方法验证分支指令已被识别。该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中，其中第一寄存器。该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

26. 发明申请

US20080059780A1 Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call 有权
标题翻译：用于模拟显式子程序调用的分支预测行为的方法和装置
公开(公告)号：US20080059780A1
公开(公告)日：2008-03-06
申请号：US11468835
申请日：2006-08-31
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F15/00
CPC分类号： G06F9/3844 , G06F9/3005 , G06F9/30058 , G06F9/30101 , G06F9/322 , G06F9/3806
摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
摘要翻译：公开了一种用于模拟显式子程序调用的分支预测行为的装置。该装置包括被配置为接收指令地址和第二输入的第一输入。第二输入被配置为接收描述与子程序的隐式子程序调用有关的指令地址的预解码信息。响应于预解码信息，该装置还包括加法器，其被配置为向定义返回地址的指令地址添加常数，使得将返回地址存储到显式子例程资源，从而便于后续分支预测返回呼叫指令。

27. 发明申请

US20070283134A1 Sliding-Window, Block-Based Branch Target Address Cache 有权
标题翻译：滑动窗口，基于块的分支目标地址缓存
公开(公告)号：US20070283134A1
公开(公告)日：2007-12-06
申请号：US11422186
申请日：2006-06-05
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Thomas Andrew Sartorius , Brian Michael Stempel
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Thomas Andrew Sartorius , Brian Michael Stempel
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based Branch Target Address Cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the Branch Target Address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在同一指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

28. 发明授权

US07624256B2 System and method wherein conditional instructions unconditionally provide output 有权
标题翻译：其中条件指令无条件地提供输出的系统和方法
公开(公告)号：US07624256B2
公开(公告)日：2009-11-24
申请号：US11106803
申请日：2005-04-14
申请人： Thomas Andrew Sartorius , James Norris Dieffenderfer , Jeffrey Todd Bridges , Kenneth Alan Dockser , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , James Norris Dieffenderfer , Jeffrey Todd Bridges , Kenneth Alan Dockser , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F13/00
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
摘要翻译：一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便它无条件地向目标提供输出。条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。评估条件。如果满足条件，则执行操作并将操作结果输出到目标。如果条件不满足，则将先前值输出到目标。后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

29. 发明授权

US07587580B2 Power efficient instruction prefetch mechanism 有权
标题翻译：高效的指令预取机制
公开(公告)号：US07587580B2
公开(公告)日：2009-09-08
申请号：US11050932
申请日：2005-02-03
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

30. 发明授权

US08943300B2 Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information 有权
标题翻译：用于使用预解码信息生成隐式和显式子程序调用返回地址预测的方法和装置
公开(公告)号：US08943300B2
公开(公告)日：2015-01-27
申请号：US12183086
申请日：2008-07-31
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/42 , G06F9/30 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3844 , G06F9/3005 , G06F9/30058 , G06F9/30101 , G06F9/322 , G06F9/3806
摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
摘要翻译：公开了一种用于模拟显式子程序调用的分支预测行为的装置。该装置包括被配置为接收指令地址和第二输入的第一输入。第二输入被配置为接收描述与子程序的隐式子程序调用有关的指令地址的预解码信息。响应于预解码信息，该装置还包括加法器，其被配置为向定义返回地址的指令地址添加常数，使得将返回地址存储到显式子例程资源，从而便于后续分支预测返回呼叫指令。

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