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21. 发明申请

US20100032804A1 HIGH VOLTAGE BIPOLAR TRANSISTOR AND METHOD OF FABRICATION 有权
标题翻译：高压双极晶体管及制造方法
公开(公告)号：US20100032804A1
公开(公告)日：2010-02-11
申请号：US12537246
申请日：2009-08-06
申请人： Scott Gerard Balster , Hiroshi Yasuda , Philipp Steinmann , Badih El-Kareh
发明人： Scott Gerard Balster , Hiroshi Yasuda , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/331 , H01L29/73
CPC分类号： H01L29/7378 , H01L21/76283 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/732
摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
摘要翻译：由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。还公开了利用本发明的双极晶体管制造IC的方法。

22. 发明授权

US08847359B2 High voltage bipolar transistor and method of fabrication 有权
标题翻译：高压双极晶体管及其制造方法
公开(公告)号：US08847359B2
公开(公告)日：2014-09-30
申请号：US12537246
申请日：2009-08-06
申请人： Scott Gerard Balster , Hiroshi Yasuda , Philipp Steinmann , Badih El-Kareh
发明人： Scott Gerard Balster , Hiroshi Yasuda , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/331 , H01L29/73 , H01L29/66 , H01L21/762 , H01L29/737 , H01L29/732 , H01L29/161 , H01L29/10
CPC分类号： H01L29/7378 , H01L21/76283 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/732
摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
摘要翻译：由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。还公开了利用本发明的双极晶体管制造IC的方法。

23. 发明授权

US08012844B2 Method of manufacturing an integrated circuit 有权
标题翻译：集成电路的制造方法
公开(公告)号：US08012844B2
公开(公告)日：2011-09-06
申请号：US12624442
申请日：2009-11-24
申请人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
发明人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/20
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.
摘要翻译：一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。

24. 发明授权

US08932942B2 Method of forming an electrical contact between a support wafer and the surface of a top silicon layer of a silicon-on-insulator wafer and an electrical device including such an electrical contact 有权
标题翻译：在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间形成电接触的方法以及包括这种电接触
公开(公告)号：US08932942B2
公开(公告)日：2015-01-13
申请号：US12729682
申请日：2010-03-23
申请人： Philipp Steinmann , Manfred Schiekofer , Michael Kraus , Thomas Scharnagl , Wolfgang Schwartz
发明人： Philipp Steinmann , Manfred Schiekofer , Michael Kraus , Thomas Scharnagl , Wolfgang Schwartz
IPC分类号： H01L29/06 , H01L21/74 , H01L21/02 , H01L21/84
CPC分类号： H01L21/743 , H01L21/02532 , H01L21/02639 , H01L21/84
摘要： Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.
摘要翻译：在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间形成电接触的方法。该方法包括将空腔蚀刻到顶部硅层和绝缘体层中。执行选择性外延步骤，以在空腔内生长直到顶部硅层的表面的硅外延层。一种电气装置，其包括根据本发明方法形成的在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间的电接触。

25. 发明授权

US06407425B1 Programmable neuron MOSFET on SOI 有权
标题翻译： SOI上的可编程神经元MOSFET
公开(公告)号：US06407425B1
公开(公告)日：2002-06-18
申请号：US09952451
申请日：2001-09-14
申请人： Jeffrey A. Babcock , Scott G. Balster , Gregory E. Howard , Angelo Pinto , Philipp Steinmann
发明人： Jeffrey A. Babcock , Scott G. Balster , Gregory E. Howard , Angelo Pinto , Philipp Steinmann
IPC分类号： H01L29788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/1203
摘要： The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.
摘要翻译：本发明描述了在SOI衬底上形成的可编程神经元MOSFET结构。多个输入电容器结构（241,231）形成在SOI衬底上。电容器（330,340）的衬底区域通过隔离结构（270）彼此完全隔离。此外，神经元MOSFET的晶体管结构（210）通过隔离结构（270）与电容器结构（241,231）完全隔离。神经元MOSFET还包括形成晶体管结构的电容器（230,240）和浮动栅极（200）的栅极结构的连续的浮动导电层（200,230和240）。

26. 发明申请

US20120112275A1 Drain Extended CMOS with Counter-Doped Drain Extension 有权
标题翻译：排水扩展CMOS与反掺杂漏极扩展
公开(公告)号：US20120112275A1
公开(公告)日：2012-05-10
申请号：US13288690
申请日：2011-11-03
申请人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
发明人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
IPC分类号： H01L29/78 , G06F17/50
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译：一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

27. 发明授权

US08592900B2 Drain extended CMOS with counter-doped drain extension 有权
标题翻译：漏极扩展扩展CMOS
公开(公告)号：US08592900B2
公开(公告)日：2013-11-26
申请号：US13288690
申请日：2011-11-03
申请人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
发明人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
IPC分类号： H01L21/00
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译：一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

28. 发明申请

US20050124079A1 Modeling process for integrated circuit film resistors 有权
标题翻译：集成电路薄膜电阻的建模过程
公开(公告)号：US20050124079A1
公开(公告)日：2005-06-09
申请号：US10728068
申请日：2003-12-04
申请人： Philipp Steinmann , Amitava Chatterjee , Doug Weiser , Roland Bucksch
发明人： Philipp Steinmann , Amitava Chatterjee , Doug Weiser , Roland Bucksch
IPC分类号： G01R31/28 , H01L21/02 , H01L27/01 , H01L21/66 , G01R31/26 , H01L21/20
CPC分类号： H01L28/20 , G01R31/2846 , G01R31/2884 , G01R31/2891 , H01L27/016
摘要： A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.
摘要翻译：提出了一种方法，其中薄膜电阻器被建模以考虑自热。该方法包括制造薄膜电阻器并表征薄膜电阻器的热阻，其中热电阻在操作期间占其自身加热。然后将热阻用于模拟使用薄膜电阻器的集成电路的模型中。

29. 发明授权

US06737326B2 Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect 有权
标题翻译：在多层金属钨插头互连中集成薄膜电阻的方法
公开(公告)号：US06737326B2
公开(公告)日：2004-05-18
申请号：US09852921
申请日：2001-05-10
申请人： Philipp Steinmann , Stuart M. Jacobsen , Louis N. Hutter , Fred D. Bailey
发明人： Philipp Steinmann , Stuart M. Jacobsen , Louis N. Hutter , Fred D. Bailey
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/32051 , H01L23/522 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.
摘要翻译：一种用于将薄膜电阻器集成到互连工艺流程中的方法，其中一个金属层用作硬掩模。在通孔（42）蚀刻和填充之后，沉积薄膜电阻器材料（62）。然后沉积金属互连层（76），包括所需的任何阻挡层。然后将金属引线（70）与薄膜电阻器（60）的形状一起蚀刻。然后去除薄膜电阻器（60）上方的金属（76）。

30. 发明申请

US20060228879A1 Thin film resistor head structure and method for reducing head resistivity variance 有权
标题翻译：薄膜电阻头结构和降低磁头电阻率方差的方法
公开(公告)号：US20060228879A1
公开(公告)日：2006-10-12
申请号：US11102100
申请日：2005-04-08
申请人： Eric Beach , Philipp Steinmann
发明人： Eric Beach , Philipp Steinmann
IPC分类号： H01L21/4763
CPC分类号： H01C7/006 , H01C17/075 , H01L23/5228 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2). Preferably, the first dummy fill layer is formed so as to extend sufficiently far beyond ends of the thin-film resistor to ensure only a negligible amount of systematic resistance error due to misalignment.
摘要翻译：制造集成电路薄膜电阻器的方法包括在衬底上形成第一电介质层（18B），并通过在第一电介质层上形成虚拟填充层（9A）提供减小其电阻率的变化的结构，以及在第一虚拟填充层上形成第二介电层（18 D）。在第二电介质层（18D）上形成薄膜电阻（2）。第一层间电介质层（21A）形成在薄膜电阻器和第二电介质层上。第一金属层（22A）形成在第一层间电介质层上并与薄膜电阻器的一部分电接触。优选地，第一虚拟填充层形成为部分的重复图案，使得重复图案相对于薄膜电阻器（2）的多个边缘对称地排列。优选地，第一虚拟填充层形成为足够远地超过薄膜电阻器的端部，以确保仅由于未对准而产生的可忽略的系统电阻误差量。

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