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21. 发明授权

US08507909B2 Measuring apparatus that includes a chip with a through silicon via, a heater having plural switches, and a stress sensor 有权
标题翻译：包括具有贯通硅通孔的芯片，具有多个开关的加热器和应力传感器的测量装置
公开(公告)号：US08507909B2
公开(公告)日：2013-08-13
申请号：US13308523
申请日：2011-11-30
申请人： Ra-Min Tain , Ming-Ji Dai , Shyh-Shyuan Sheu , Chih-Sheng Lin , Shih-Hsien Wu
发明人： Ra-Min Tain , Ming-Ji Dai , Shyh-Shyuan Sheu , Chih-Sheng Lin , Shih-Hsien Wu
IPC分类号： H01L23/58
CPC分类号： G01B7/18 , G01L1/18 , G01L1/2206 , H01L2224/16145
摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.
摘要翻译：提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。第一电路层设置在第一表面上。第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。第二电路层设置在第二表面上。第一加热器包括串联连接以产生热量的多个第一开关。

22. 发明授权

US08031515B2 Data programming circuits and memory programming methods 有权
标题翻译：数据编程电路和存储器编程方法
公开(公告)号：US08031515B2
公开(公告)日：2011-10-04
申请号：US12275223
申请日：2008-11-21
申请人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Pei-Chia Chiang , Wen-Pin Lin
发明人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Pei-Chia Chiang , Wen-Pin Lin
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.
摘要翻译：提供了一种用于将写入数据存储到存储单元中的数据编程电路。数据编程电路包括控制电路和电流产生电路。控制电路根据写入数据生成控制信号。电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

23. 发明申请

US20090135645A1 Data Programming Circuits And Memory Programming Methods 有权
标题翻译：数据编程电路和存储器编程方法
公开(公告)号：US20090135645A1
公开(公告)日：2009-05-28
申请号：US12275223
申请日：2008-11-21
申请人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Pei-Chia Chiang , Wen-Pin Lin
发明人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Pei-Chia Chiang , Wen-Pin Lin
IPC分类号： G11C7/00 , G11C11/56
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.
摘要翻译：提供了一种用于将写入数据存储到存储单元中的数据编程电路。数据编程电路包括控制电路和电流产生电路。控制电路根据写入数据生成控制信号。电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

24. 发明申请

US20090080243A1 DEVICE CONTROLLING PHASE CHANGE STORAGE ELEMENT AND METHOD THEREOF 有权
标题翻译：装置控制相变存储元件及其方法
公开(公告)号：US20090080243A1
公开(公告)日：2009-03-26
申请号：US12142724
申请日：2008-06-19
申请人： Pei-Chia Chiang , Shyh-Shyuan Sheu , Lieh-Chiu Lin , Wen-Pin Lin
发明人： Pei-Chia Chiang , Shyh-Shyuan Sheu , Lieh-Chiu Lin , Wen-Pin Lin
IPC分类号： G11C11/00
CPC分类号： G11C5/14 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0078
摘要： Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.
摘要翻译：控制相变存储元件的装置和增加相变存储元件的可靠性的方法。本发明引入了第一操作模式和第二操作模式。参考相变存储元件在第一操作模式中强制写入电流以达到理想的导通时段。在第二操作模式中，本发明基于参考相变存储元件的电阻产生适当的导通周期，并将写入电流强制到受控相变存储元件中以达到适当的导通周期。

25. 发明申请

US20090010047A1 WRITING CIRCUIT FOR A PHASE CHANGE MEMORY 有权
标题翻译：相位变化记忆的写入电路
公开(公告)号：US20090010047A1
公开(公告)日：2009-01-08
申请号：US11957044
申请日：2007-12-14
申请人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Pei-Chia Chiang
发明人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Pei-Chia Chiang
IPC分类号： G11C11/56
CPC分类号： G11C13/0061 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.
摘要翻译：提供了相变存储器写入电路。该电路包括写入路径和快速写入控制单元。写入路径还包括电流驱动单元，第一开关器件和相变存储器单元。电流驱动单元耦合到高电压源并输出驱动电流。第一开关装置由第一控制信号控制。快速写入控制单元耦合到写入路径以向写入路径提供写入电压。当第一开关装置关闭时，快速写入控制单元将写入电压输出到写入路径。当第一开关装置接通时，快速写入控制单元停止向写入路径输出写入电压。

26. 发明申请

US20080157826A1 VOLTAGE DRIVING CIRCUIT 审中-公开
标题翻译：电压驱动电路
公开(公告)号：US20080157826A1
公开(公告)日：2008-07-03
申请号：US11739114
申请日：2007-04-24
申请人： Ming-Daw Chen , Shyh-Shyuan Sheu , Wei-Chun Chang , Keng-Li Su
发明人： Ming-Daw Chen , Shyh-Shyuan Sheu , Wei-Chun Chang , Keng-Li Su
IPC分类号： H03K3/00
CPC分类号： G09G3/3648 , G09G2300/0465 , G09G2300/0809 , G09G2300/0823 , G09G2300/0857
摘要： A voltage driving circuit, suitable for being used in a pixel driving circuit, includes a storage unit for receiving a single-end data input signal and outputting a first voltage signal and a second voltage signal according to a content of the data input signal. The first voltage signal and the second voltage signal have different voltage levels, and the voltage levels are a high voltage level and a low voltage level, which have been adjusted to a driving-voltage requirement satisfying subsequent operations. A switch control unit receives the first voltage signal and the second voltage signal and outputs an output-voltage signal at an output terminal based on a determination from at least one control signal. The output-voltage signal is the high voltage level or the low voltage level.
摘要翻译：适用于像素驱动电路的电压驱动电路包括：存储单元，用于接收单端数据输入信号，并根据数据输入信号的内容输出第一电压信号和第二电压信号。第一电压信号和第二电压信号具有不同的电压电平，并且电压电平是已经被调整到满足后续操作的驱动电压要求的高电压电平和低电压电平。开关控制单元接收第一电压信号和第二电压信号，并且基于来自至少一个控制信号的确定在输出端输出输出电压信号。输出电压信号为高电平或低电平。

27. 发明授权

US08508983B2 Nonvolatile static random access memory cell and memory circuit 有权
标题翻译：非易失性静态随机存取存储单元和存储电路
公开(公告)号：US08508983B2
公开(公告)日：2013-08-13
申请号：US13230865
申请日：2011-09-13
申请人： Min-Chuan Wang , Pi-Feng Chiu , Shyh-Shyuan Sheu
发明人： Min-Chuan Wang , Pi-Feng Chiu , Shyh-Shyuan Sheu
IPC分类号： G11C11/00
CPC分类号： G11C14/0054
摘要： A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.
摘要翻译：提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由切换线的切换信号控制，以将第一存储装置和第二存储装置导入相同的位线或相同的补充位线。

28. 发明申请

US20130121058A1 CIRCUIT AND METHOD FOR CONTROLLING WRITE TIMING OF A NON-VOLATILE MEMORY 有权
标题翻译：用于控制非易失性存储器的写入时序的电路和方法
公开(公告)号：US20130121058A1
公开(公告)日：2013-05-16
申请号：US13345740
申请日：2012-01-08
申请人： Pi-Feng Chiu , Shyh-Shyuan Sheu , Wen-Pin Lin , Chih-He Lin
发明人： Pi-Feng Chiu , Shyh-Shyuan Sheu , Wen-Pin Lin , Chih-He Lin
IPC分类号： G11C11/00
CPC分类号： G11C8/16 , G11C7/14 , G11C8/08 , G11C8/18 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0078
摘要： A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.
摘要翻译：提供了用于控制非易失性存储器的写入定时的电路和方法。该方法包括以下步骤。首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。存储单元存储具有不同电阻状态的数据状态。通过定时控制线将写时序输入到存储单元。接下来，基于时钟信号和控制信号来生成写入定时。写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

29. 发明授权

US08331134B2 Non-volatile static random access memory and operation method thereof 有权
标题翻译：非易失性静态随机存取存储器及其操作方法
公开(公告)号：US08331134B2
公开(公告)日：2012-12-11
申请号：US12853301
申请日：2010-08-10
申请人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
发明人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C14/0054 , G11C14/009
摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.
摘要翻译：提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二开关的第二端子分别连接到第一和第二位线。第一和第二开关的控制端子连接到字线。第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二NVM的第二端子分别连接到第一和第二位线。第一和第二NVM的使能端子连接到使能线。

30. 发明授权

US08300449B2 Resistive random access memory and verifying method thereof 有权
标题翻译：电阻随机存取存储器及其验证方法
公开(公告)号：US08300449B2
公开(公告)日：2012-10-30
申请号：US12955657
申请日：2010-11-29
申请人： Chih-He Lin , Shyh-Shyuan Sheu , Wen-Pin Lin , Pei-Chia Chiang
发明人： Chih-He Lin , Shyh-Shyuan Sheu , Wen-Pin Lin , Pei-Chia Chiang
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/79
摘要： A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.
摘要翻译：提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。验证方法包括以下步骤：确定电阻式存储单元是否通过验证。在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子信号向电阻存储单元写入反向电压。

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