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21. 发明申请

US20130339695A1 ASYNCHRONOUS LOOKAHEAD SECOND LEVEL BRANCH TARGET BUFFER 有权
标题翻译：不寻常的LOOKAHEAD第二级分支目标缓冲区
公开(公告)号：US20130339695A1
公开(公告)日：2013-12-19
申请号：US13524311
申请日：2012-06-15
申请人： James J. Bonanno , Akash V. Giri , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Akash V. Giri , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30047 , G06F9/30145 , G06F9/3808
摘要： Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer.
摘要翻译：实施例涉及异步前瞻分层分支预测。一个方面包括用于异步前瞻分层分支预测的系统。该系统包括耦合到处理电路的第一级分支目标缓冲器和第二级分支目标缓冲器。处理电路被配置为执行一种方法。该方法包括接收搜索请求以定位与搜索地址相关联的分支预测信息，并且搜索与第一级分支目标缓冲器中的搜索请求相对应的条目。基于对与搜索请求相对应的第一级分支目标缓冲器中的匹配条目未定位，启动辅助搜索以定位具有与搜索请求对应的存储区域的第二级分支目标缓冲器中的条目。基于在二级分支目标缓冲器中定位条目，从第二级分支目标缓冲器执行条目的批量传送。

22. 发明申请

US20130339693A1 SECOND-LEVEL BRANCH TARGET BUFFER BULK TRANSFER FILTERING 有权
标题翻译：第二级分支目标缓冲区大容量传输过滤
公开(公告)号：US20130339693A1
公开(公告)日：2013-12-19
申请号：US13524306
申请日：2012-06-15
申请人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30047
摘要： Embodiments relate to second-level branch target buffer bulk transfer filtering. An aspect includes a system for second-level branch target buffer bulk transfer filtering. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving branch target buffer miss indicators, receiving instruction cache miss indicators, and recording information about the branch target buffer miss indicators and the instruction cache miss indicators in search trackers. Based on detecting, by the processing circuit, a search tracker representing a correlated pair of the branch target buffer miss indicators and the instruction cache miss indicators, the search tracker is activated by the processing circuit to perform a bulk transfer from the second-level branch target buffer to the first-level branch target buffer.
摘要翻译：实施例涉及二级分支目标缓冲器批量传输过滤。一个方面包括用于二级分支目标缓冲区大容量传输过滤的系统。该系统包括耦合到处理电路的第一级分支目标缓冲器和第二级分支目标缓冲器。处理电路被配置为执行一种方法。该方法包括接收分支目标缓存器未命中指示符，接收指令高速缓存未命中指示符，以及记录关于分支目标缓存器未命中指示符和搜索跟踪器中的指令高速缓存未命中指示的信息。基于由处理电路检测表示分支目标缓冲器未命中指示符的相关对的指针和指示高速缓存未命中指示符的搜索跟踪器，由处理电路激活搜索跟踪器，以从第二级分支目标缓冲区到第一级分支目标缓冲区。

23. 发明授权

US09430241B2 Semi-exclusive second-level branch target buffer 有权
标题翻译：半独立二级分支目标缓冲区
公开(公告)号：US09430241B2
公开(公告)日：2016-08-30
申请号：US13524314
申请日：2012-06-15
申请人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30145 , G06F9/3808
摘要： Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a system for a semi-exclusive second-level branch target buffer. The system includes a first-level branch target buffer (BTB1), a branch target buffer preload table (BTBP), and a second-level branch target buffer (BTB2) coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes performing a search to locate entries in the BTB2 having a memory region corresponding to a search request. Based on locating entries in the BTB2, a bulk transfer of located entries is performed from the BTB2 to the BTBP. A state associated with the located entries is updated to encourage exclusivity between the BTB1 and the BTB2. Based on transferring a BTBP entry from the BTBP to the BTB1, a BTB1 entry is evicted from the BTB1. The evicted BTB1 entry is transferred from the BTB1 to the BTB2.
摘要翻译：实施例涉及半独有的第二级分支目标缓冲器。一个方面包括用于半独占二级分支目标缓冲器的系统。该系统包括耦合到处理电路的第一级分支目标缓冲器（BTB1），分支目标缓冲器预加载表（BTBP）和第二级分支目标缓冲器（BTB2）。处理电路被配置为执行一种方法。该方法包括执行搜索以定位具有对应于搜索请求的存储区域的BTB2中的条目。基于BTB2中的定位条目，从BTB2到BTBP执行定位条目的批量传输。更新与定位条目关联的状态，以鼓励BTB1和BTB2之间的排他性。基于将BTBP条目从BTBP转移到BTB1，BTB1条目从BTB1被移出。驱逐的BTB1条目从BTB1转移到BTB2。

24. 发明申请

US20130332716A1 BRANCH TARGET BUFFER PRELOAD TABLE 有权
标题翻译：分支目标缓冲器PRELOAD TABLE
公开(公告)号：US20130332716A1
公开(公告)日：2013-12-12
申请号：US13492997
申请日：2012-06-11
申请人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.
摘要翻译：实施例涉及使用分支目标缓冲器预载表。一方面包括接收搜索请求以定位与分支指令相关联的分支预测信息。在分支目标缓冲器和分支目标缓冲器预加载表中并行执行与搜索请求对应的条目的搜索。基于在与搜索请求相对应的分支目标缓冲器预加载表中找到匹配条目，并且未能在分支目标缓冲器中定位匹配条目，则选择受害者条目以在分支目标缓冲器中覆盖。从分支目标缓冲器中的分支目标缓冲器预加载表接收匹配条目的分支预测信息。分支目标缓冲器中的受害者条目被匹配条目的分支预测信息重写。

25. 发明授权

US09152510B2 Hardware recovery in multi-threaded processor 有权
公开(公告)号：US09152510B2
公开(公告)日：2015-10-06
申请号：US13548448
申请日：2012-07-13
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/1479 , G06F11/1438
摘要： A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

26. 发明申请

US20130332670A1 PROCESS IDENTIFIER-BASED CACHE DATA TRANSFER 有权
标题翻译：基于过程识别器的高速缓存数据传输
公开(公告)号：US20130332670A1
公开(公告)日：2013-12-12
申请号：US13493636
申请日：2012-06-11
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/08
CPC分类号： G06F17/30982 , G06F12/0817 , G06F12/12
摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.
摘要翻译：本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

27. 发明申请

US20130191678A1 IN SITU PROCESSOR RE-CHARACTERIZATION 有权
标题翻译：在现场处理器重新表征
公开(公告)号：US20130191678A1
公开(公告)日：2013-07-25
申请号：US13353544
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F1/08
CPC分类号： G06F11/24 , G06F1/206 , G06F1/32 , G06F1/324
摘要： A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.
摘要翻译：提供重新表征处理，其调整处理器的一个或多个操作参数以改善处理器的健康状况（例如，减少错误）。参数包括电压和/或时钟频率，例如。处理器可以是对其执行重新表征处理的非活动或活动处理器。在一个实例中，它由硬件控制器实时执行。

28. 发明申请

US20110320774A1 OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
标题翻译：操作控制作为分支机构的功能
公开(公告)号：US20110320774A1
公开(公告)日：2011-12-29
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译：一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制控制单元被配置为执行方法。该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

29. 发明授权

US08930950B2 Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors 有权
标题翻译：在计算环境中迁移线程的管理，以将多个线程模式处理器转换为单线程模式处理器
公开(公告)号：US08930950B2
公开(公告)日：2015-01-06
申请号：US13353550
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4856 , G06F9/505 , G06F9/5088
摘要： Threads of a computing environment are managed to improve system performance. Threads are migrated between processors to take advantage of single thread processing mode, when possible. As an example, inactive threads are migrated from one or more processors, potentially freeing-up one or more processors to execute an active thread. Active threads are migrated from one processor to another to transform multiple threading mode processors to single thread mode processors.
摘要翻译：管理计算环境的线程以提高系统性能。线程在处理器之间迁移，以尽可能利用单线程处理模式。作为示例，非活动线程从一个或多个处理器迁移，潜在地释放一个或多个处理器以执行活动线程。活动线程从一个处理器迁移到另一个处理器，以将多个线程模式处理器转换为单线程模式处理器。

30. 发明授权

US08806139B2 Cache set replacement order based on temporal set recording 有权
标题翻译：基于时间设置记录的缓存集替换顺序
公开(公告)号：US08806139B2
公开(公告)日：2014-08-12
申请号：US13354894
申请日：2012-01-20
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/12
CPC分类号： G06F12/0875 , G06F12/126
摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.
摘要翻译：提供了用于高速缓存的高速缓存管理的技术。处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。命中位置字段包括与缓存中的数据元素相关的分层位置。

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