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21. 发明授权

US06172544B2 Timing signal generation circuit for semiconductor test system 失效
标题翻译：用于半导体测试系统的定时信号发生电路
公开(公告)号：US06172544B2
公开(公告)日：2001-01-09
申请号：US09257907
申请日：1999-02-25
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： H03Q514
CPC分类号： G01R31/31922
摘要： A timing signal generation circuit to be used in a semiconductor test system which is not affected by voltage changes or temperature changes. The timing signal generation circuit includes a first reference clock, a coarse delay circuit provided with the first reference clock for generating a coarse delay signal having a delay time of an integer multiple of one cycle of the first reference clock on the basis of coarse delay data provided thereto, a second reference clock having a frequency which is predetermined times higher than that of the first reference clock, a first fine delay circuit provided with the second reference clock for producing a fine delay time which is an integer multiple of one cycle of the second reference clock but is smaller than the one cycle of the first reference clock, a selector circuit for selectively applying the coarse delay signal to the first fine delay circuit at an input specified by a select signal, and a second fine delay circuit for receiving an output signal of the first fine delay circuit and adding a delay time which is smaller than the one cycle of the second reference clock to the output signal based on fine delay data. The coarse delay circuit and the second fine delay circuit are formed in a first semiconductor integrated circuit while the first fine delay circuit and the selector circuit are formed in a second semiconductor integrated circuit which has a higher operation speed than that of the first semiconductor integrated circuit.
摘要翻译：一种定时信号发生电路，用于不受电压变化或温度变化影响的半导体测试系统。定时信号产生电路包括第一参考时钟，粗略延迟电路，设置有第一参考时钟，用于基于粗延迟数据产生具有第一参考时钟的一个周期的整数倍的延迟时间的粗延迟信号提供具有比第一参考时钟的频率高预定次数的频率的第二参考时钟;第一精细延迟电路，设置有第二参考时钟，用于产生作为第一参考时钟的一个周期的整数倍的精细延迟时间第二参考时钟，但是小于第一参考时钟的一个周期;选择器电路，用于在由选择信号指定的输入处选择性地将粗延迟信号施加到第一精细延迟电路;以及第二精细延迟电路，输出第一精细延迟电路的输出信号，并将比第二参考时钟的一个周期小的延迟时间加到ou 基于精细延迟数据的输入信号。粗略延迟电路和第二精细延迟电路形成在第一半导体集成电路中，而第一精细延迟电路和选择器电路形成在具有比第一半导体集成电路高的操作速度的第二半导体集成电路中。

22. 发明授权

US4310802A Logical waveform generator 失效
标题翻译：逻辑波形发生器
公开(公告)号：US4310802A
公开(公告)日：1982-01-12
申请号：US69348
申请日：1979-08-24
申请人： Yoshichika Ichimiya , Tsuneta Sudo , Hiromi Maruyama , Shigeru Sugamori , Susumu Sumida , Takashi Tokuno
发明人： Yoshichika Ichimiya , Tsuneta Sudo , Hiromi Maruyama , Shigeru Sugamori , Susumu Sumida , Takashi Tokuno
IPC分类号： G06F11/22 , G01R31/3183 , G01R31/319 , G06F1/06 , H03K5/135 , H03K5/156 , H03K5/22
CPC分类号： G01R31/31922 , H03K5/156 , G01R31/31928
摘要： Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.
摘要翻译：输入逻辑数据由每个时隙的数据分割电路顺序划分成n个数据列，每个数据块具有n个时隙长度。可以任意定时的时钟信号由时钟分频电路划分成n个时钟信号，这些时钟信号在相位上分离一个时隙并且以n个时隙的周期发生。在逻辑电路中，划分的时钟信号由对应的分割数据串进行控制，并且受控时钟信号由复用电路进行时间复用，从而获得输入逻辑数据已被时钟信号定时的输出数据。

23. 发明授权

US06445208B1 Power source current measurement unit for semiconductor test system 失效
标题翻译：半导体测试系统的电源电流测量单元
公开(公告)号：US06445208B1
公开(公告)日：2002-09-03
申请号：US09544058
申请日：2000-04-06
申请人： Shigeru Sugamori
发明人： Shigeru Sugamori
IPC分类号： G01R3136
CPC分类号： G01R31/31921 , G01R31/3004 , G01R31/3191
摘要： A semiconductor test system having a power source current measurement unit for measuring a power source current of a device under test with high speed and accuracy. The power source measurement unit includes a DA converter for generating a source voltage, an operational amplifier for forming a negative feedback loop and supplying the source voltage to a power pin of the device under test thereby supplying a power source current to the power pin, a voltage amplifier for amplifying a voltage representing the amount of power source current supplied to the device under test, an integration circuit for integrating an output signal of the voltage amplifier for a predetermined integration time, and an AD converter for converting an output signal of the integration circuit to a digital signal after the integration time.
摘要翻译：一种具有电源电流测量单元的半导体测试系统，用于以高速度和精确度测量被测器件的电源电流。电源测量单元包括用于产生源电压的DA转换器，用于形成负反馈回路的运算放大器，并将源电压提供给被测器件的电源引脚，从而向电源引脚提供电源电流; 电压放大器，用于放大表示提供给被测器件的电源电流量的电压，用于对预定积分时间积分电压放大器的输出信号的积分电路和用于转换积分时间的输出信号的AD转换器电路到数字信号后的积分时间。

24. 发明授权

US4414665A Semiconductor memory device test apparatus 失效
标题翻译：半导体存储器件测试装置
公开(公告)号：US4414665A
公开(公告)日：1983-11-08
申请号：US206902
申请日：1980-11-14
申请人： Kenji Kimura , Shigeru Sugamori , Kohji Ishikawa , Naoaki Narumi
发明人： Kenji Kimura , Shigeru Sugamori , Kohji Ishikawa , Naoaki Narumi
IPC分类号： G11C29/56 , G06F11/26
CPC分类号： G11C29/56
摘要： A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.
摘要翻译：受测试的存储器件由模式发生器产生的地址访问，以便在其中写入数据并读出要与预期数据进行比较的数据，并且比较结果在读取之后被相同的地址存储在故障地址存储器中从中输出地址的内容。当通过比较检测到不一致时，它是计数的; 然而，如果从故障寻址存储器读出的数据是故障数据，则计数操作被禁止。当计数值超过预定值时，产生故障信号。测试结束后，操作地址计数器，通过地址计数器的内容读取故障地址存储器，当从输出读出检测到故障数据时，将地址计数器的内容取入中央处理器。

25. 发明授权

US4270116A High speed data logical comparison device 失效
标题翻译：高速数据逻辑比较装置
公开(公告)号：US4270116A
公开(公告)日：1981-05-26
申请号：US69347
申请日：1979-08-24
申请人： Yoshichika Ichimiya , Tsuneta Sudo , Hiromi Maruyama , Shigeru Sugamori , Susumu Sumida , Masao Shimizu , Toshiaki Wakita
发明人： Yoshichika Ichimiya , Tsuneta Sudo , Hiromi Maruyama , Shigeru Sugamori , Susumu Sumida , Masao Shimizu , Toshiaki Wakita
IPC分类号： G01R31/28 , G06F7/02 , G06F7/04 , G06F11/22
CPC分类号： G06F7/02
摘要： Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.
摘要翻译：参考逻辑数据由每个时隙的数据分割电路在空间上划分，并且分割的数据被转换成数据，每个数据具有连续的有效周期。通过比较器比较分割和转换的参考数据和输入逻辑数据，以检测它们是否彼此一致。用于确定比较定时的时钟信号也被时钟信号分频电路划分为n个时钟信号，这些n个时钟信号相移一个时隙并且以n个时隙的周期发生。通过这些分开的时钟信号，从比较输出电路中取出与其相对应的比较器的输出。

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