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21. 发明申请

US20070153104A1 PIXEL ARRAY, IMAGING SENSOR INCLUDING THE PIXEL ARRAY AND DIGITAL CAMERA INCLUDING THE IMAGING SENSOR 有权
标题翻译：像素阵列，成像传感器，包括像素阵列和数码相机，包括成像传感器
公开(公告)号：US20070153104A1
公开(公告)日：2007-07-05
申请号：US11275417
申请日：2005-12-30
申请人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau , Richard Rassel
发明人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau , Richard Rassel
IPC分类号： H04N9/04
CPC分类号： H04N9/045
摘要： A pixel array in an image sensor, the image sensor and a digital camera including the image sensor. The image sensor includes a pixel array with colored pixels and unfiltered (color filter-free) pixels. Each unfiltered pixel occupies one or more array locations. The colored pixels may be arranged in uninterrupted rows and columns with unfiltered pixels disposed between the uninterrupted rows and columns. The image sensor may in CMOS with the unfiltered pixels reducing low-light noise and improving low-light sensitivity.
摘要翻译：图像传感器中的像素阵列，图像传感器和包括图像传感器的数字照相机。图像传感器包括具有彩色像素和未滤波（无滤色器）像素的像素阵列。每个未过滤的像素占据一个或多个阵列位置。彩色像素可以布置在不间断的行和列中，其中未过滤的像素布置在不间断的行和列之间。图像传感器可以在CMOS中，未滤色像素降低低光噪声并改善低光灵敏度。

22. 发明申请

US20070235780A1 BODY POTENTIAL IMAGER CELL 有权
标题翻译：身体潜像成像细胞
公开(公告)号：US20070235780A1
公开(公告)日：2007-10-11
申请号：US11765485
申请日：2007-06-20
申请人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau
发明人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau
IPC分类号： H01L31/0352
CPC分类号： H01L27/14643 , H01L27/14603 , H01L27/14609 , H01L27/14679
摘要： An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.
摘要翻译：成像电路，成像传感器和成像方法。所述成像单元电路包括一个或多个成像单元电路，每个成像单元电路包括：晶体管，具有浮动体，用于响应于浮体暴露于电磁辐射而保持在浮体中产生的电荷; 用于偏置晶体管的装置，其中晶体管的输出响应于电磁辐射; 以及用于选择性地将浮动体连接到复位电压源的装置。

23. 发明申请

US20070202635A1 MULTI-ORIENTATION SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE, AND METHOD OF FABRICATING SAME 有权
标题翻译：多导体半导体绝缘体（SOI）衬底及其制造方法
公开(公告)号：US20070202635A1
公开(公告)日：2007-08-30
申请号：US11276366
申请日：2006-02-27
申请人： John Ellis-Monaghan , Mark Jaffe
发明人： John Ellis-Monaghan , Mark Jaffe
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/76264 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045
摘要： The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.
摘要翻译：本发明涉及绝缘体上半导体（SOI）衬底结构，其包含直接位于绝缘体层上的不同晶体取向的表面半导体区域。本发明还涉及制造这种SOI衬底结构的方法，通过直接在多取向体半导体衬底上生长绝缘体层，该绝缘体层包括直接位于半导体基底层上的不同晶体取向的表面半导体区域，以及去除半导体基底从而形成包括直接位于绝缘体层上的不同晶体取向的表面半导体区域的多取向SOI衬底结构。

24. 发明申请

US20060192233A1 BODY POTENTIAL IMAGER CELL 有权
标题翻译：身体潜像成像细胞
公开(公告)号：US20060192233A1
公开(公告)日：2006-08-31
申请号：US10906625
申请日：2005-02-28
申请人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau
发明人： John Ellis-Monaghan , Mark Jaffe , Alain Loiseau
IPC分类号： H01L27/148
CPC分类号： H01L27/14643 , H01L27/14603 , H01L27/14609 , H01L27/14679
摘要： An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.
摘要翻译：成像电路，成像传感器和成像方法。所述成像单元电路包括一个或多个成像单元电路，每个成像单元电路包括：晶体管，具有浮动体，用于响应于浮体暴露于电磁辐射而保持在浮体中产生的电荷; 用于偏置晶体管的装置，其中晶体管的输出响应于电磁辐射; 以及用于选择性地将浮动体连接到复位电压源的装置。

25. 发明申请

US20050272195A1 Integrated circuit having pairs of parallel complementary finfets 失效
标题翻译：具有并联互补鳍对的集成电路
公开(公告)号：US20050272195A1
公开(公告)日：2005-12-08
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
发明人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/8232
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

26. 发明申请

US20050001273A1 INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS 有权
标题翻译：具有并联补偿器件对的集成电路
公开(公告)号：US20050001273A1
公开(公告)日：2005-01-06
申请号：US10604206
申请日：2003-07-01
申请人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
发明人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L33/00
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

27. 发明申请

US20050101072A1 Transistor structure with thick recessed source/drain structures and fabrication process of same 失效
公开(公告)号：US20050101072A1
公开(公告)日：2005-05-12
申请号：US11007843
申请日：2004-12-09
申请人： Andres Bryant , Mark Jaffe
发明人： Andres Bryant , Mark Jaffe
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/00 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/42384 , H01L29/66772 , H01L29/66795
摘要： An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

28. 发明授权

US07528427B2 Pixel sensor cell having asymmetric transfer gate with reduced pinning layer barrier potential 有权
标题翻译：具有不对称传输门的像素传感器单元具有降低的钉扎层屏障电势
公开(公告)号：US07528427B2
公开(公告)日：2009-05-05
申请号：US11668555
申请日：2007-01-30
申请人： Jeffrey Gambino , Mark Jaffe
发明人： Jeffrey Gambino , Mark Jaffe
IPC分类号： H01L31/062 , H01L27/148
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1463
摘要： A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge transfer caused by the pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。公开了一种像素传感器单元，其包括非对称传输门，用于提供钉扎层，该钉扎层的边缘与电荷收集阱的边缘相距离栅极沟道区域的距离更远。降低了由钉扎层引起的电荷转移的电位障碍。

29. 发明申请

US20070132067A1 WAFER-TO-WAFER ALIGNMENTS 失效
标题翻译： WAFER-WAFER对准
公开(公告)号：US20070132067A1
公开(公告)日：2007-06-14
申请号：US11557668
申请日：2006-11-08
申请人： Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Stephen Luce , Edmund Sprogis
发明人： Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Stephen Luce , Edmund Sprogis
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。第一个方向基本上平行于共同的表面。

30. 发明申请

US20080179639A1 PIXEL SENSOR CELL HAVING ASYMMETRIC TRANSFER GATE AND METHOD OF FORMING 有权
标题翻译：具有不对称转移门的像素传感器单元及其形成方法
公开(公告)号：US20080179639A1
公开(公告)日：2008-07-31
申请号：US11668555
申请日：2007-01-30
申请人： Jeffrey Gambino , Mark Jaffe
发明人： Jeffrey Gambino , Mark Jaffe
IPC分类号： H01L31/113
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/1463
摘要： A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge transfer caused by the pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。公开了一种像素传感器单元，其包括非对称传输门，用于提供钉扎层，该钉扎层的边缘与电荷收集阱的边缘相距离栅极沟道区域的距离更远。降低了由钉扎层引起的电荷转移的电位障碍。

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