专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06653155B2 Integrated circuit devices including a resistor pattern and methods for manufacturing the same 有权
标题翻译：包括电阻图案的集成电路器件及其制造方法
公开(公告)号：US06653155B2
公开(公告)日：2003-11-25
申请号：US10051908
申请日：2002-01-17
申请人： Seok-Jun Won , Young-Wook Park
发明人： Seok-Jun Won , Young-Wook Park
IPC分类号： H01L2100
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/10894
摘要： Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred &mgr;&OHgr;·cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.
摘要翻译：提供了用于形成包括具有所需电阻值的电阻图案的集成电路器件的方法。在集成电路基板上形成低电阻层。在与集成电路基板相对的低电阻层上形成绝缘层。在与低电阻层相反的绝缘层上形成可能具有至少约百μΩ·cm的电阻率的高电阻层。低电阻层，绝缘层和高电阻层在集成电路基板的区域中限定电阻器图案。还提供了包括由方法提供的电阻器图案的集成电路器件，并且还提供了用于形成与电阻器图案的金属触点的方法。

22. 发明授权

US07902090B2 Method of forming a layer on a semiconductor substrate 失效
标题翻译：在半导体衬底上形成层的方法
公开(公告)号：US07902090B2
公开(公告)日：2011-03-08
申请号：US12212466
申请日：2008-09-17
申请人： Jung-Hun Seo , Young-Wook Park , Jin-Gi Hong
发明人： Jung-Hun Seo , Young-Wook Park , Jin-Gi Hong
IPC分类号： H01L21/336
CPC分类号： C23C16/45544 , C23C16/34 , C23C16/45565 , C23C16/45589
摘要： In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.
摘要翻译：在通过同一腔室中的ALD工艺和CVD工艺形成用于半导体器件的薄层的方法中，将半导体衬底引入到处理室中，将喷头与衬底之间的间隔调整到第一间隙距离。通过ALD工艺在第一温度下在衬底上形成第一层。喷淋头和基板之间的间隔被额外地调整到第二间隙距离，并且通过CVD工艺在第二温度下在第一层上形成第二层。因此，薄层具有良好的电流特性，提高了半导体器件的制造能力。

23. 发明授权

US07509501B2 Cryptographic apparatus for supporting multiple modes 有权
标题翻译：用于支持多种模式的加密设备
公开(公告)号：US07509501B2
公开(公告)日：2009-03-24
申请号：US10744125
申请日：2003-12-23
申请人： Tae-Gon Park , Kyung-Wan Nam , Young-Wook Park
发明人： Tae-Gon Park , Kyung-Wan Nam , Young-Wook Park
IPC分类号： G06F11/30 , G06F12/14 , H04L9/32
CPC分类号： H04L9/0637 , H04L2209/12 , H04L2209/20
摘要： The present invention relates to a cryptographic apparatus for encrypting data stored in a memory. The cryptographic apparatus of the present invention operates in the ECB, CBC, CBC-MAC, counter and OCB modes using small and simple elements. The cryptographic apparatus minimizes data communication between CPU and the cryptographic apparatus to improve the performance of the communication system. On the other hand, the input buffer and output buffer of the cryptographic apparatus are configured to store at least two blocks respectively, so that the performance of the cryptographic apparatus is maximized. Furthermore, the cryptographic apparatus supports zero-padding, so that the process of the CPU is minimized.
摘要翻译：本发明涉及一种加密存储在存储器中的数据的密码装置。本发明的密码装置使用小而简单的元件在ECB，CBC，CBC-MAC，计数器和OCB模式下工作。密码装置使CPU与密码装置之间的数据通信最小化，以提高通信系统的性能。另一方面，密码装置的输入缓冲器和输出缓冲器被配置为分别存储至少两个块，使得密码装置的性能最大化。此外，密码装置支持零填充，使得CPU的处理最小化。

24. 发明申请

US20070085207A1 Pad structure, method of forming a pad structure, semiconductor device having a pad structure and method of manufacturing a semiconductor device 审中-公开
标题翻译：衬垫结构，形成衬垫结构的方法，具有衬垫结构的半导体器件和制造半导体器件的方法
公开(公告)号：US20070085207A1
公开(公告)日：2007-04-19
申请号：US11497279
申请日：2006-08-02
申请人： Woo-Sung Lee , Young-Wook Park , Nam-Kyu Kim , Bong-Hyun Kim , Man-Sug Kang
发明人： Woo-Sung Lee , Young-Wook Park , Nam-Kyu Kim , Bong-Hyun Kim , Man-Sug Kang
IPC分类号： H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/28562 , H01L21/76831 , H01L21/76879 , H01L21/76889 , H01L21/76895 , H01L21/823425 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： A pad structure, a method of forming a pad structure, a semiconductor device having a pad structure and a method of manufacturing a semiconductor device are disclosed. The pad structure may include a first pad, a second pad, a third pad and/or a spacer. The first pad may contact a contact region on a substrate. The first pad may include doped polysilicon. The second pad may contact the first pad. The second pad may include a metal silicide or a metal silicongermanium. The third pad may contact the second pad. The third pad may include a conductive material (e.g., doped polysilicon, a metal or a metal nitride). The spacer may be formed on sidewalls of the second and the third pads.
摘要翻译：公开了一种焊盘结构，形成焊盘结构的方法，具有焊盘结构的半导体器件和制造半导体器件的方法。垫结构可以包括第一垫，第二垫，第三垫和/或间隔件。第一焊盘可以接触衬底上的接触区域。第一焊盘可以包括掺杂多晶硅。第二垫可以接触第一垫。第二焊盘可以包括金属硅化物或金属硅石。第三垫可以接触第二垫。第三焊盘可以包括导电材料（例如，掺杂多晶硅，金属或金属氮化物）。间隔件可以形成在第二和第三焊盘的侧壁上。

25. 发明授权

US07129174B2 Methods of fabricating a semiconductor substrate for reducing wafer warpage 失效
公开(公告)号：US07129174B2
公开(公告)日：2006-10-31
申请号：US10806521
申请日：2004-03-23
申请人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
发明人： Won-Jin Kim , Young-Wook Park , Jeong-Do Ryu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0209 , H01L21/302 , H01L21/6708 , H01L21/76895 , H01L27/10844 , H01L27/10882 , H01L29/7842
摘要： Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

26. 发明申请

US20060054087A1 Process chamber for manufacturing seminconductor devices 审中-公开
标题翻译：用于制造半导体器件的过程室
公开(公告)号：US20060054087A1
公开(公告)日：2006-03-16
申请号：US11000941
申请日：2004-12-02
申请人： Jung-Hun Seo , Yun-Ho Choi , Young-Wook Park , Jeong-Tae Kim
发明人： Jung-Hun Seo , Yun-Ho Choi , Young-Wook Park , Jeong-Tae Kim
IPC分类号： C23C16/00
CPC分类号： C23C16/4401
摘要： The present invention is directed to a plasma process chamber capable of maintaining a high vacuum in the idle state. The present invention maintains a high vacuum in the idle state and prevents a contamination of the wafer transferred into the process chamber.
摘要翻译：本发明涉及能够在空闲状态下保持高真空的等离子体处理室。本发明在怠速状态下保持高真空并且防止转移到处理室中的晶片的污染。

27. 发明申请

US20060000411A1 Method of forming a layer on a semiconductor substrate and apparatus for performing the same 失效
标题翻译：在半导体基板上形成层的方法及其制造方法
公开(公告)号：US20060000411A1
公开(公告)日：2006-01-05
申请号：US11154110
申请日：2005-06-15
申请人： Jung-Hun Seo , Young-Wook Park , Jin-Gi Hong
发明人： Jung-Hun Seo , Young-Wook Park , Jin-Gi Hong
IPC分类号： C23C16/00
CPC分类号： C23C16/45544 , C23C16/34 , C23C16/45565 , C23C16/45589
摘要： In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.
摘要翻译：在通过同一腔室中的ALD工艺和CVD工艺形成用于半导体器件的薄层的方法中，将半导体衬底引入到处理室中，将喷头与衬底之间的间隔调整到第一间隙距离。通过ALD工艺在第一温度下在衬底上形成第一层。喷淋头和基板之间的间隔被额外地调整到第二间隙距离，并且通过CVD工艺在第二温度下在第一层上形成第二层。因此，薄层具有良好的电流特性，提高了半导体器件的制造能力。

28. 发明申请

US20050140110A1 Multi-link rear suspension system 有权
标题翻译：多连杆后悬挂系统
公开(公告)号：US20050140110A1
公开(公告)日：2005-06-30
申请号：US11005405
申请日：2004-12-06
申请人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
发明人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
IPC分类号： B60G3/20 , B60G3/06 , B60G3/12 , B60G7/00 , B60G7/02 , B60G13/06 , B60G15/06 , B62D21/00 , F16F3/10 , F16F15/04 , F16F15/08
CPC分类号： B60G3/202 , B60G7/001 , B60G7/008 , B60G2200/1442 , B60G2200/184 , B60G2202/12 , B60G2202/24 , B60G2204/1244 , B60G2204/143 , B60G2204/148 , B60G2204/15 , B60G2206/50
摘要： A knuckle is minimized in size to be located in an internal space of a rear wheel. An upper arm is disposed lower than a conventional double wishbone type and one end of the upper arm is secured to the knuckle. A shock absorber couples at a lower end thereof to the knuckle by passing through a space between a lower arm and assist arm. This configuration thus constructed greatly increases the space of the trunk room, reduces noise by minimizing the transmission of road impact and vibration, and improves ride comfort as well as braking stability and turn stability.
摘要翻译：转向节的尺寸被最小化以位于后轮的内部空间中。上臂布置成低于传统的双叉骨型，并且上臂的一端固定在转向节上。减震器通过穿过下臂和辅助臂之间的空间在其下端处连接到转向节。这样构造大大增加了行李箱的空间，通过最小化道路冲击和振动的传递来降低噪音，并且提高乘坐舒适度以及制动稳定性和转向稳定性。

29. 发明授权

US07243934B2 Multi-link rear suspension system 有权
标题翻译：多连杆后悬挂系统
公开(公告)号：US07243934B2
公开(公告)日：2007-07-17
申请号：US11005405
申请日：2004-12-06
申请人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
发明人： Un-Koo Lee , Sang-Ho Lee , Hyung-Bae Jang , Young-Wook Park
IPC分类号： B60G3/12
CPC分类号： B60G3/202 , B60G7/001 , B60G7/008 , B60G2200/1442 , B60G2200/184 , B60G2202/12 , B60G2202/24 , B60G2204/1244 , B60G2204/143 , B60G2204/148 , B60G2204/15 , B60G2206/50
摘要： A knuckle is minimized in size to be located in an internal space of a rear wheel. An upper arm is disposed lower than a conventional double wishbone type and one end of the upper arm is secured to the knuckle. A shock absorber couples at a lower end thereof to the knuckle by passing through a space between a lower arm and assist arm. This configuration thus constructed greatly increases the space of the trunk room, reduces noise by minimizing the transmission of road impact and vibration, and improves ride comfort as well as braking stability and turn stability.
摘要翻译：转向节的尺寸被最小化以位于后轮的内部空间中。上臂布置成低于传统的双叉骨型，并且上臂的一端固定在转向节上。减震器通过穿过下臂和辅助臂之间的空间在其下端处连接到转向节。这样构造大大增加了行李箱的空间，通过最小化道路冲击和振动的传递来降低噪音，并且提高乘坐舒适度以及制动稳定性和转向稳定性。

30. 发明申请

US20060115954A1 Methods of manufacturing a capacitor and a semiconductor device 审中-公开
标题翻译：制造电容器和半导体器件的方法
公开(公告)号：US20060115954A1
公开(公告)日：2006-06-01
申请号：US11265937
申请日：2005-11-03
申请人： Woo-Seok Shim , Young-Wook Park , Jung-Hyeon Lee , Kwang-Sub Yoon , Chul-Ho Kim , Tae-Jin Park
发明人： Woo-Seok Shim , Young-Wook Park , Jung-Hyeon Lee , Kwang-Sub Yoon , Chul-Ho Kim , Tae-Jin Park
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： In methods of manufacturing a capacitor and a semiconductor device, a mold layer is formed on a substrate having a contact plug. The mold layer includes an opening exposing the contact plug. A conductive layer is formed on the contact plug, an inner sidewall of the opening and the mold layer. A photoresist pattern is formed to substantially fill the opening. A cylindrical lower electrode is formed by partially removing the conductive layer. The mold layer is selectively removed while the photoresist pattern prevents damage to the lower electrode, the contact plug and the substrate. The photoresist pattern is removed, and then a dielectric layer and an upper electrode are sequentially formed on the lower electrode. Damage to the lower electrode and the contact plug are effectively prevented due to the presence of the photoresist pattern during selective removal of the mold layer.
摘要翻译：在制造电容器和半导体器件的方法中，在具有接触插塞的基板上形成模层。模具层包括露出接触塞的开口。在接触插塞，开口的内侧壁和模具层上形成导电层。形成光致抗蚀剂图案以基本上填充开口。通过部分去除导电层形成圆柱形下电极。选择性地去除模具层，同时光刻胶图案防止损坏下部电极，接触插塞和基板。去除光致抗蚀剂图案，然后在下电极上依次形成电介质层和上电极。由于在选择性去除模具层期间存在光致抗蚀剂图案，因此有效地防止了下电极和接触插塞的损坏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式