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21. 发明授权

US06307396B1 Low-consumption TTL-CMOS input buffer stage 失效
标题翻译：低功耗TTL-CMOS输入缓冲级
公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
申请人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
发明人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译：低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和第二或地面参考。有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

22. 发明申请

US20080028182A1 ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE 有权
公开(公告)号：US20080028182A1
公开(公告)日：2008-01-31
申请号：US11829527
申请日：2007-07-27
申请人： Hyungsang LEE , Dae Sik SONG , Jacopo Mulatti
发明人： Hyungsang LEE , Dae Sik SONG , Jacopo Mulatti
IPC分类号： G06F12/06
CPC分类号： G11C8/04 , G11C16/08
摘要： An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

23. 发明申请

US20070297228A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20070297228A1
公开(公告)日：2007-12-27
申请号：US11759649
申请日：2007-06-07
申请人： Dae Song , Jaeseok Park , Jacopo Mulatti
发明人： Dae Song , Jaeseok Park , Jacopo Mulatti
IPC分类号： G06F13/28 , G11C14/00 , G06F12/00 , G11C11/34 , G06F13/00 , G11C16/06
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.
摘要翻译：非易失性存储器件在记录或修改存储的数据时实现程序例程，随后是程序验证程序。非易失性存储器件可以包括用于存储数据的存储器单元阵列，感测节点和用于选择性地将存储器单元阵列的位线连接到感测节点的选通电路。非易失性存储器件还可以包括耦合到感测节点的页缓冲器。页面缓冲器可以包括用于存储要写入非易失性存储器件的数据的主锁存器，用于存储提供在非易失性存储器件的输入线上的数据的高速缓冲存储器，用于通过源衬垫传输到主锁存器中，静态锁存器通过源极线连接到主锁存器，并通过辅助开关连接到高速缓存锁存器，并用于在主锁存器和高速缓存锁存器之间传送数据。在执行程序例程和程序验证程序期间，高速缓存锁存器可以与源线隔离。

24. 发明授权

US07002399B2 Basic stage for a charge pump circuit 失效
标题翻译：电荷泵电路的基本阶段
公开(公告)号：US07002399B2
公开(公告)日：2006-02-21
申请号：US10402852
申请日：2003-03-28
申请人： Giovanni Nuzzarello , Jacopo Mulatti
发明人： Giovanni Nuzzarello , Jacopo Mulatti
IPC分类号： G05F3/16
CPC分类号： H02M3/073 , G11C5/145 , H02M2003/071
摘要： A basic stage for a charge pump circuit having at least an input terminal and an output terminal and comprising: at least a first inverter inserted between said input and output terminals and comprising a first complementary pair of transistors, defining a first internal node, at least a second inverter inserted between said input and output terminals and comprising a second complementary pair of transistors, defining a second internal node, respective first and second capacitors connected to said first and second internal nodes and receiving first and second driving signals; the first and second pairs of transistors having the control terminals cross-connected to the second and first internal nodes. Advantageously, the basic stage comprises at least a first biasing structure connected to the first and second internal nodes and comprising first and second biasing transistors, which are respectively coupled to said first and second inverters.
摘要翻译：一种用于至少具有输入端子和输出端子的电荷泵电路的基本步骤，包括：至少插入在所述输入和输出端子之间的第一反相器，并且包括第一互补对晶体管，至少限定第一内部节点第二反相器插入在所述输入和输出端之间，并且包括限定第二内部节点的第二互补对晶体管，连接到所述第一和第二内部节点的相应的第一和第二电容器，以及接收第一和第二驱动信号; 所述第一和第二对晶体管具有与第二和第一内部节点交叉连接的控制端子。有利地，基本级包括连接到第一和第二内部节点的至少第一偏置结构，并且包括分别耦合到所述第一和第二逆变器的第一和第二偏置晶体管。

25. 发明授权

US6153914A Output circuit for integrated circuits 有权
标题翻译：集成电路输出电路
公开(公告)号：US6153914A
公开(公告)日：2000-11-28
申请号：US170788
申请日：1998-10-13
申请人： Jacopo Mulatti , Stefano Zanardi , Carla Maria Golla , Armando Conci
发明人： Jacopo Mulatti , Stefano Zanardi , Carla Maria Golla , Armando Conci
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H01L27/0928 , H01L27/0251 , H03K17/162 , H03K19/00361 , Y10S257/901
摘要： An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.
摘要翻译：用于集成电路的输出电路包括分别通过第一和第二电连接路径串联连接在集成电路外部的第一外部电压和第二外部电压之间的第一晶体管和第二晶体管。第一晶体管用于将集成电路的输出线传送到第一外部电压，而第二晶体管用于将集成电路的外部线路传送到第二外部电压。第二晶体管形成在形成在第一导电类型的衬底中的第二导电类型的第二阱内的第一导电类型的第一阱内。第二导电类型的第二阱通过与第一电连接路径不同的第三电连接路径连接到第一外部电压。

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