专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090179264A1 LDMOS INTEGRATED SCHOTTKY DIODE 有权
标题翻译： LDMOS集成肖特基二极管
公开(公告)号：US20090179264A1
公开(公告)日：2009-07-16
申请号：US12014581
申请日：2008-01-15
申请人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
发明人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
IPC分类号： H01L27/06 , H01L29/872
CPC分类号： H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/40 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7806 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.
摘要翻译：半导体器件包括具有第一导电类型的衬底和形成在衬底上并具有下表面和上表面的半导体层。横向扩散的金属氧化物半导体（LDMOS）晶体管器件形成在衬底上，并且包括第一导电类型的源极区域和形成在靠近半导体的上表面的半导体层中的第一导电类型的漏极延伸区域以及将漏极延伸区域与衬底电连接的漏极接触。肖特基二极管形成在衬底之上，并且包括形成在靠近上表面的半导体层中的至少一个第一导电类型的掺杂区域，形成具有至少一个掺杂区域的肖特基势垒的阳极接触器和阴极接触器与阳极接触件横向间隔开并将至少一个掺杂区域电连接到衬底。

22. 发明申请

US20070215939A1 Quasi-vertical LDMOS device having closed cell layout 有权
标题翻译：具有闭孔布局的准垂直LDMOS器件
公开(公告)号：US20070215939A1
公开(公告)日：2007-09-20
申请号：US11376470
申请日：2006-03-14
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/4238 , H01L29/7802 , H01L29/7835
摘要： A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.
摘要翻译：低压功率器件包括多个准垂直LDMOS器件单元。导电沟槽沉积片通过外延层形成并且与每个单元中的源极和漏极区域中的一个相邻。沟槽沉积片将所选择的源极和漏极区之一电耦合到衬底，以将电流从沟道耦合到衬底。所得到的器件在覆盖前表面的金属电极和形成在晶片背面的第二电极之间呈现垂直的电流。设备单元被布置成闭孔配置。

23. 发明申请

US20070034944A1 Power LDMOS transistor 有权
公开(公告)号：US20070034944A1
公开(公告)日：2007-02-15
申请号：US11202968
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/94 , H01L31/00 , H01L29/76
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/4933
摘要： A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.

24. 发明授权

US08629019B2 Method of forming self aligned contacts for a power MOSFET 有权
标题翻译：形成功率MOSFET自对准触点的方法
公开(公告)号：US08629019B2
公开(公告)日：2014-01-14
申请号：US10254385
申请日：2002-09-24
申请人： Robert Q. Xu , Jacek Korec
发明人： Robert Q. Xu , Jacek Korec
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L29/407 , H01L29/7813
摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.
摘要翻译：公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。该方法还包括凹陷形成在沟槽中的多晶硅插塞，其位于有源区域中，以在多晶硅插塞之上形成凹陷，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成一个绝缘体，从而施加第四张照片抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦的表面氧化物按钮。此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

25. 发明授权

US09136060B2 Precision high-frequency capacitor formed on semiconductor substrate 有权
标题翻译：精密高频电容器形成于半导体基板上
公开(公告)号：US09136060B2
公开(公告)日：2015-09-15
申请号：US11966965
申请日：2007-12-28
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/20 , H01G4/33 , H01G4/38 , H01L49/02 , H01L29/94 , H01L29/66 , H01L23/48
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
摘要翻译：一种在半导体衬底中制造电容器的方法。掺杂半导体衬底以具有低电阻率。与第一电极绝缘的第二电极形成在前侧表面上，并且通过金属填充的通孔连接到背侧表面。可以省略通孔，并且第二电极可以与衬底电接触，或者可以形成在介电层的顶部，从而产生一对串联电容器。电容器的ESD保护由形成在与电容器并联连接的衬底中的一对相反方向的二极管提供。电容增加同时保持低有效的串联电阻。电极包括多个指状物，其与另一个电极的指状物交叉指向。电容器采用具有其他电容器的晶片级工艺制造，其中电容器通过切割技术彼此分离。

26. 发明授权

US08367500B1 Method of forming self aligned contacts for a power MOSFET 失效
标题翻译：形成功率MOSFET自对准触点的方法
公开(公告)号：US08367500B1
公开(公告)日：2013-02-05
申请号：US10378766
申请日：2003-03-03
申请人： Robert Q. Xu , Jacek Korec
发明人： Robert Q. Xu , Jacek Korec
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L29/407 , H01L29/7813
摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.
摘要翻译：公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。该方法还包括凹陷形成在沟槽中的多晶硅塞，其位于有源区域中以在多晶硅插塞之上形成凹槽，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成的绝缘体填充凹陷，施加第四张照片抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦表面氧化物按钮。此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

27. 发明申请

US20110176247A1 PRECISION HIGH-FREQUENCY CAPACITOR FORMED ON SEMICONDUCTOR SUBSTRATE 有权
标题翻译：精密高频电容器在半导体衬底上形成
公开(公告)号：US20110176247A1
公开(公告)日：2011-07-21
申请号：US13075752
申请日：2011-03-30
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H02H9/00 , H01L21/20 , H01L29/92
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.
摘要翻译：精密高频电容器包括形成在半导体衬底的前侧表面上的电介质层和位于电介质层顶部的第一电极。半导体衬底是重掺杂的，因此具有低电阻率。与第一电极绝缘的第二电极也形成在前侧表面上。在一个实施例中，第二电极通过金属填充的通孔连接到衬底背面上的导电材料层。在替代实施例中，省略通孔，并且第二电极与衬底电接触或者形成在电介质层的顶部，从而产生一对串联电容器。电容器的ESD保护可以由形成在衬底中并与电容器并联连接的一对相反方向的二极管提供。为了在保持低有效串联电阻的同时增加电容器的电容，每个电极可以包括与另一个电极的指状物交叉的多个指状物。电容器优选与晶片上的许多其它电容器同时地以晶片级工艺制造，然后通过常规的切割技术将电容器彼此分离。

28. 发明授权

US07952145B2 MOS transistor device in common source configuration 有权
标题翻译： MOS晶体管器件的共同源配置
公开(公告)号：US07952145B2
公开(公告)日：2011-05-31
申请号：US11676618
申请日：2007-02-20
申请人： Jacek Korec , Stephen L. Colino
发明人： Jacek Korec , Stephen L. Colino
IPC分类号： H01L29/34
CPC分类号： H02J9/04 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/7835 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/16 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/3025 , Y10T307/461 , Y10T307/469 , Y10T307/625 , Y10T307/696 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的第一p沟道横向扩散金属氧化物半导体（LDMOS）晶体管和形成在半导体衬底上的附加p沟道LDMOS晶体管。第一漏极和栅电极形成在衬底上并且耦合到第一LDMOS晶体管。另外的漏极和栅电极形成在衬底上并耦合到第二LDMOS晶体管。用于第一和第二LDMOS晶体管的公共源电极也形成在衬底上。

29. 发明申请

US20110042742A1 STRUCTURES OF AND METHODS OF FABRICATING TRENCH-GATED MIS DEVICES 审中-公开
标题翻译：制造TRENCH-GATED MIS装置的结构和方法
公开(公告)号：US20110042742A1
公开(公告)日：2011-02-24
申请号：US12917378
申请日：2010-11-01
申请人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

30. 发明申请

US20100295152A1 Precision high-frequency capacitor formed on semiconductor substrate 有权
标题翻译：精密高频电容器形成于半导体基板上
公开(公告)号：US20100295152A1
公开(公告)日：2010-11-25
申请号：US11601501
申请日：2006-11-16
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L29/92
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.
摘要翻译：精密高频电容器包括形成在半导体衬底的前侧表面上的电介质层和位于电介质层顶部的第一电极。半导体衬底是重掺杂的，因此具有低电阻率。与第一电极绝缘的第二电极也形成在前侧表面上。在一个实施例中，第二电极通过金属填充的通孔连接到衬底背面上的导电材料层。在替代实施例中，省略通孔，并且第二电极与衬底电接触或者形成在电介质层的顶部，从而产生一对串联电容器。电容器的ESD保护可以由形成在衬底中并与电容器并联连接的一对相反方向的二极管提供。为了在保持低有效串联电阻的同时增加电容器的电容，每个电极可以包括与另一个电极的指状物交叉的多个指状物。电容器优选与晶片上的许多其它电容器同时地以晶片级工艺制造，然后通过常规的切割技术将电容器彼此分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式