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21. 发明授权

US07392339B2 Partial bank DRAM precharge 有权
标题翻译：部分银行DRAM预充电
公开(公告)号：US07392339B2
公开(公告)日：2008-06-24
申请号：US10732635
申请日：2003-12-10
申请人： Howard S. David
发明人： Howard S. David
IPC分类号： G06F12/00
CPC分类号： G11C11/4076 , G11C11/4094
摘要： A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second implementation the command precharges one quarter of the banks. The power drawn by the upper or lower bank precharge on the eight bank DRAM is the same as the power drawn by an “all bank” precharge on a four bank DRAM, without requiring the precharge period to be extended.
摘要翻译： “部分PRECHARGE”部分用于对多行DRAM中的一部分存储体进行预充电。在第一个实施中，命令预充电一半的银行。在第二个实施中，命令预充电四分之一的银行。在八组DRAM上由上或下组预充电所得的功率与在四组DRAM上的“全库”预充电所得的功率相同，而不需要延长预充电周期。

22. 发明授权

US07036053B2 Two dimensional data eye centering for source synchronous data transfers 失效
标题翻译：用于源同步数据传输的二维数据眼心
公开(公告)号：US07036053B2
公开(公告)日：2006-04-25
申请号：US10324864
申请日：2002-12-19
申请人： John F. Zumkehr , John L. Bryan , Howard S. David , Klaus Ruff
发明人： John F. Zumkehr , John L. Bryan , Howard S. David , Klaus Ruff
IPC分类号： G01R31/3183
CPC分类号： G11C7/1066 , G11C7/1051 , G11C29/02 , G11C2207/2254
摘要： A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.
摘要翻译：用于优化源同步时钟参考信号定时以从存储器件（例如，DDR SDRAM）捕获数据的方法包括进行迭代二维数据眼搜索以优化源同步时钟参考信号（例如，DQS）的延迟，。本发明的实施例涉及在两个维度中调整每个设备的延迟以获得最佳余量：使距离数据眼壁的距离最大化并且使接口上的噪声容限最大化。在改变DQS延迟定时和噪声容限的同时进行迭代数据眼搜索。

23. 发明授权

US06976121B2 Apparatus and method to track command signal occurrence for DRAM data transfer 失效
标题翻译：用于跟踪DRAM数据传输的命令信号发生的装置和方法
公开(公告)号：US06976121B2
公开(公告)日：2005-12-13
申请号：US10058838
申请日：2002-01-28
申请人： Narendra S. Khandekar , Michael W. Williams , Howard S. David
发明人： Narendra S. Khandekar , Michael W. Williams , Howard S. David
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G11C7/1063 , G06F13/1668 , G11C7/1051
摘要： An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.
摘要翻译：已经公开了用于跟踪用于DRAM数据传送的命令信号发生的装置和方法。在一个实施例中，该装置包括耦合到数据总线的接口，该数据总线在接口和一个或多个存储器件之间传送数据，以及一个逻辑单元，以产生命令发生信号，以识别何时发出命令信号其中响应于所述命令发生信号，标志信号的转换和对应于所述一个存储器件的片选信号而完成所述一个或多个存储器件之一上的一组数据传送操作。已经要求和描述了其它实施例。

24. 发明授权

US06938129B2 Distributed memory module cache 有权
标题翻译：分布式内存模块缓存
公开(公告)号：US06938129B2
公开(公告)日：2005-08-30
申请号：US10039648
申请日：2001-12-31
申请人： Howard S. David
发明人： Howard S. David
IPC分类号： G06F12/00 , G06F12/08 , G06F13/16
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0864 , G06F13/1684
摘要： One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules.
摘要翻译：分布式存储器模块高速缓存的一个实施例包括在存储器通道的存储器控制器端实现的标签存储器和相关逻辑。存储器控制器通过点对点接口耦合到至少一个存储器模块。数据高速缓存和相关联的逻辑位于每个存储器模块上的一个或多个缓冲器组件中。

25. 发明授权

US06931505B2 Distributed memory module cache command formatting 失效
标题翻译：分布式内存模块缓存命令格式化
公开(公告)号：US06931505B2
公开(公告)日：2005-08-16
申请号：US10039651
申请日：2001-12-31
申请人： Howard S. David
发明人： Howard S. David
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0862 , G06F2212/6022
摘要： One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The memory controller communicates with the memory module via a variety of commands. Included in these commands are an activate command and a cache fetch command. A command is delivered from the memory controller to the memory modules over four transfer periods. The activate command and the cache fetch command have formats that differ only in the information delivered in the fourth transfer period. A read command and a read and preload command similarly differ only in the information delivered over the fourth transfer period. Differentiating different commands during the fourth transfer period allows the maximum amount of time to process tag look-ups.
摘要翻译：分布式存储器模块高速缓存的一个实施例包括在存储器通道的存储器控制器端实现的标签存储器和相关逻辑。存储器控制器通过点对点接口耦合到至少一个存储器模块。数据高速缓存和相关联的逻辑位于每个存储器模块上的一个或多个缓冲器组件中。存储器控制器通过各种命令与存储器模块进行通信。这些命令中包含一个activate命令和一个cache fetch命令。在四个传输周期内，一个命令从存储器控制器传送到存储器模块。激活命令和缓存获取命令具有仅在第四传送周期中传递的信息不同的格式。读取命令和读取和预加载命令在第四个传输周期中传递的信息类似地不同。在第四个传输期间区分不同的命令允许处理标签查找的最大时间量。

26. 发明授权

US08375241B2 Method and system to improve the operations of a registered memory module 有权
标题翻译：改进注册内存模块操作的方法和系统
公开(公告)号：US08375241B2
公开(公告)日：2013-02-12
申请号：US12417534
申请日：2009-04-02
申请人： James W. Alexander , Kuljit S. Bains , Howard S. David
发明人： James W. Alexander , Kuljit S. Bains , Howard S. David
IPC分类号： G06F1/00 , G06F1/12 , G06F12/00 , G11C11/34 , G11C11/00 , G11C5/14
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译：一种改善注册内存模块操作的方法和系统。在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。

27. 发明授权

US08122265B2 Power management using adaptive thermal throttling 有权
标题翻译：电源管理采用自适应热调节
公开(公告)号：US08122265B2
公开(公告)日：2012-02-21
申请号：US11648253
申请日：2006-12-29
申请人： Sivakumar Radhakrishnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
发明人： Sivakumar Radhakrishnan , Suneeta Sah , William H. Nale , Rami Naqib , Howard S. David , Rajat Agarwal
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203
摘要： In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括调度器，发射机，接收机和控制电路。时间表调度要在芯片外部发送的信号，并且发送器在芯片外发送调度信号。接收器接收包括具有与芯片外的温度有关的温度信息的信号的信号。控制电路选择性地限制可以在一系列较小窗口内调度的多个命令，同时检查靠近包括许多较小窗口的较大窗口的结论的温度信息。描述其他实施例。

28. 发明授权

US07626884B2 Optimizing mode register set commands 有权
标题翻译：优化模式寄存器设置命令
公开(公告)号：US07626884B2
公开(公告)日：2009-12-01
申请号：US11978811
申请日：2007-10-30
申请人： Christopher Cox , Howard S. David
发明人： Christopher Cox , Howard S. David
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/1045 , G11C7/22 , G11C11/4076
摘要： In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency.
摘要翻译：在一个实施例中，本发明包括一种用于产生模式寄存器组（MRS）解码信号以识别注册的DIMM存储器的寄存器装置中MRS命令的存在的方法，将MRS解码信号延迟预定的延迟并禁用地址使用延迟MRS解码信号进行反转，在预定数量的时钟周期内从第一命令定时频率切换到第二命令定时频率，向DRAM设备的模式寄存器执行MRS命令，并切换回到第一命令定时频率。

29. 发明申请

US20090085604A1 MULTIPLE ADDRESS OUTPUTS FOR PROGRAMMING THE MEMORY REGISTER SET DIFFERENTLY FOR DIFFERENT DRAM DEVICES 有权
标题翻译：用于编程存储器寄存器的多个地址输出不同于不同的DRAM器件
公开(公告)号：US20090085604A1
公开(公告)日：2009-04-02
申请号：US11863106
申请日：2007-09-27
申请人： Howard S. David
发明人： Howard S. David
IPC分类号： H03K19/003
CPC分类号： G11C7/1045 , G11C5/04
摘要： A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inline memory module (DIMM). Additionally, the method also includes programming a second ODT value into a second plurality of additional DRAM devices. The second plurality of additional DRAM devices are also located on the DIMM. The method also specifies that the first and second ODT values are not the same value.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法包括将第一接通终端（ODT）值编程到第一多个动态随机存取存储器（DRAM）设备中。第一组多个DRAM器件位于双列直插存储器模块（DIMM）上。另外，该方法还包括将第二ODT值编程到第二多个附加DRAM器件中。第二组多个附加DRAM设备也位于DIMM上。该方法还指定第一个和第二个ODT值不是相同的值。

30. 发明授权

US07389387B2 Distributed memory module cache writeback 有权
标题翻译：分布式内存模块缓存回写
公开(公告)号：US07389387B2
公开(公告)日：2008-06-17
申请号：US10039596
申请日：2001-12-31
申请人： Howard S. David
发明人： Howard S. David
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0804 , G06F2212/304 , G06F2212/3042
摘要： One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. Writes to a memory module are stored in the data cache which allows the writes to be postponed until the DRAM on the memory module is not busy.
摘要翻译：分布式存储器模块高速缓存的一个实施例包括在存储器通道的存储器控制器端实现的标签存储器和相关逻辑。存储器控制器通过点对点接口耦合到至少一个存储器模块。数据高速缓存和相关联的逻辑位于每个存储器模块上的一个或多个缓冲器组件中。对存储器模块的写入存储在数据高速缓存中，这允许写入被推迟直到存储器模块上的DRAM不忙。

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