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21. 发明授权

US6077749A Method of making dual channel gate oxide thickness for MOSFET transistor design 失效
标题翻译：制造MOSFET晶体管设计的双通道栅氧化层厚度的方法
公开(公告)号：US6077749A
公开(公告)日：2000-06-20
申请号：US34117
申请日：1998-03-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/42368 , H01L29/518 , H01L29/66583 , Y10S438/981
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. The oxide having the greater thickness is formed adjacent a source or drain region of the device, and the oxide with the lesser thickness is formed adjacent the other one of the source or drain regions. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO.sub.2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO.sub.2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译：具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。具有较大厚度的氧化物邻近器件的源极或漏极区域形成，并且具有较小厚度的氧化物形成为邻近源极或漏极区域中的另一个。优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。氮注入抑制氧气环境中的二氧化硅生长速率。因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。可以沉积栅极氧化物层而不是生长栅极氧化物层。在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。然后可以注入半导体衬底以形成掺杂的漏极和源极区域。然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

22. 发明授权

US5943585A Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen 失效
标题翻译：沟槽隔离结构，其具有布置在掺入氮气的氧化物衬垫上的低K电介质间隔物
公开(公告)号：US5943585A
公开(公告)日：1999-08-24
申请号：US994253
申请日：1997-12-19
申请人： Charles E. May , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Charles E. May , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76237
摘要： A process is provided for forming a trench isolation structure which includes dielectric spacers composed of a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. In an embodiment, a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner which is incorporated with nitrogen atoms is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner and the masking layer. The dielectric material is anisotropically etched to form sidewall spacers upon the oxide liner. A fill oxide is then formed within the trench upon the sidewall spacers and the oxide liner. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide. The trench isolation structure is less is likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.
摘要翻译：提供了一种用于形成沟槽隔离结构的工艺，该沟槽隔离结构包括由介电材料构成的电介质隔离层，介电材料具有相对低的介电常数K，大约小于3.8。由沟槽隔离结构隔开的与K成正比的有源区之间的电容因此减小。在一个实施例中，在形成有掩模层的半导体衬底内蚀刻沟槽。掺有氮原子的氧化物衬垫在沟槽的侧壁和基底上热生长。一层低K电介质材料沉积在氧化物衬垫和掩蔽层两侧。电介质材料被各向异性地蚀刻以在氧化物衬垫上形成侧壁间隔物。然后在沟槽内在侧壁间隔物和氧化物衬垫上形成填充氧化物。所形成的沟槽隔离结构包括介于氧化物衬垫和填充氧化物之间的低K电介质材料。在采用隔离结构的随后的集成电路的操作期间，沟槽隔离结构较少可能经历电流泄漏。

23. 发明授权

US5915195A Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure 失效
标题翻译：离子注入工艺，以改善浅沟槽隔离结构边缘处的栅氧化层质量
公开(公告)号：US5915195A
公开(公告)日：1999-06-22
申请号：US977795
申请日：1997-11-25
申请人： H. Jim Fulford, Jr. , Charles E. May
发明人： H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/76 , H01L21/28 , H01L21/316 , H01L21/762 , H01L29/423 , H01L29/51 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28202 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L21/76235 , H01L21/76237 , H01L29/42368 , H01L29/518
摘要： A semiconductor fabrication process comprising forming a dielectric on an upper surface of a single crystal silicon substrate. A trench mask is then patterned on an upper surface of the dielectric. The trench mask exposes portions of the dielectric situated over portions of the isolation region. Exposed portions of the dielectric are then removed and portions of the silicon within the isolation region are also removed to form an isolation trench within the silicon substrate. This formation results in the formation of corners in the silicon substrate where the upper surface of the silicon substrate intersects with sidewalls of the isolation trench. Localized damage is then created in regions proximal to these corners of the silicon substrate preferably through the use of one or more ion implantation processes performed at implant angles in excess of approximately 30.degree. C. During the subsequent formation of a liner oxide on the sidewalls and floor of the isolation trench, the localized damage region results in a higher oxidation rate of the silicon substrate proximal to the silicon substrate corners. This higher oxidation rate results in a rounding or smoothing of the silicon corners thereby resulting in a less severe gradient between the silicon active region and the isolation trench.
摘要翻译：一种半导体制造工艺，包括在单晶硅衬底的上表面上形成电介质。然后在电介质的上表面上形成沟槽掩模。沟槽掩模暴露位于隔离区域的部分之上的电介质的部分。然后去除电介质的暴露部分，并且去除隔离区内的硅的部分，以在硅衬底内形成隔离沟槽。这种形成导致硅衬底中的角部的形成，其中硅衬底的上表面与隔离沟槽的侧壁相交。然后在硅衬底的这些角部附近的区域中产生局部损伤，优选地通过使用在超过约30℃的植入角度下进行的一个或多个离子注入工艺。在随后在侧壁上形成衬垫氧化物隔离沟槽的地板，局部损伤区域导致硅衬底接近硅衬底拐角的较高的氧化速率。这种较高的氧化速率导致硅角的倒圆或平滑，从而导致硅有源区和隔离沟之间的较不严格的梯度。

24. 发明授权

US06451657B1 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效
标题翻译：具有由横向扩散的氮植入物限定的超短沟道长度的晶体管
公开(公告)号：US06451657B1
公开(公告)日：2002-09-17
申请号：US09781044
申请日：2001-02-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译：公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。在轻掺杂的半导体衬底上形成栅氧化层。然后在栅极氧化物层上沉积栅极导体层。栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。热退火降低了无氮区域的宽度。然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

25. 发明授权

US6150708A Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density 有权
标题翻译：先进的CMOS电路，利用晶片表面的两侧增加电路密度
公开(公告)号：US6150708A
公开(公告)日：2000-11-21
申请号：US191305
申请日：1998-11-13
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L25/00
CPC分类号： H01L21/8221 , H01L27/0694 , H01L27/092
摘要： An integrated circuit employing both sides of a base substrate or wafer and a method of making the same are provided. In one aspect, the integrated circuit includes a base substrate that has a first side and a second side opposite the first side. The first side has a first semiconductor layer and a first isolation structure positioned thereon wherein the first side surrounds the first semiconductor layer. The second side has a second semiconductor layer and a second isolation structure positioned thereon wherein the second isolation structure surrounds the second semiconductor layer. A first circuit device is positioned on the first semiconductor layer. A second circuit device is positioned on the second semiconductor layer. The method enables simultaneous processing of both sides of a given wafer. Fabrication efficiency is increased through higher throughput and much higher yields per wafer.
摘要翻译：提供采用基底或晶片两侧的集成电路及其制造方法。一方面，集成电路包括具有第一侧和与第一侧相对的第二侧的基底基板。第一侧具有第一半导体层和位于其上的第一隔离结构，其中第一侧围绕第一半导体层。第二侧具有第二半导体层和位于其上的第二隔离结构，其中第二隔离结构围绕第二半导体层。第一电路器件位于第一半导体层上。第二电路器件位于第二半导体层上。该方法能够同时处理给定晶片的两侧。通过更高的产量和更高的每片晶圆产量提高制造效率。

26. 发明授权

US6087705A Trench isolation structure partially bound between a pair of low K dielectric structures 失效
标题翻译：沟槽隔离结构部分地结合在一对低K电介质结构之间
公开(公告)号：US6087705A
公开(公告)日：2000-07-11
申请号：US195592
申请日：1998-11-18
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/762 , H01L29/00 , H01L23/58
CPC分类号： H01L21/76237
摘要： A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate. The sidewall spacers permit the lateral width of the trench to be reduced below the minimum lateral dimension definable using lithography. A trench dielectric is formed within the trench such that the upper portion of the dielectric is bound by the sidewall spacers on opposite ends. The resulting trench isolation structure is less likely to experience current leakage when operating an ensuing integrated circuit which employs the isolation structure.
摘要翻译：提供了一种用于形成具有邻近沟槽隔离结构的相对侧边缘布置的相对低的介电常数的介电结构的工艺。在一个实施例中，通过布置在半导体衬底上的掩模层垂直蚀刻开口，从而暴露衬底的表面。使用光刻法在掩模层上形成图案化的光致抗蚀剂层，以限定待蚀刻的区域。由低K电介质材料制成的侧壁隔离物形成在开口内的掩蔽层的相对的侧壁表面上。通过在开口内CVD沉积电介质材料并各向异性地蚀刻电介质材料形成侧壁间隔物，直到材料的预定厚度仅保留在掩模层侧壁表面上为止。此后，在衬底内形成限定在侧壁间隔物的暴露的横向边缘之间的沟槽。侧壁间隔件允许将沟槽的横向宽度减小到使用光刻可定义的最小横向尺寸以下。在沟槽内形成沟槽电介质，使得电介质的上部由相对端上的侧壁间隔件结合。当使用隔离结构的随后集成电路进行操作时，所得到的沟槽隔离结构不太可能经历电流泄漏。

27. 发明授权

US6078078A V-gate transistor 失效
标题翻译： V型栅极晶体管
公开(公告)号：US6078078A
公开(公告)日：2000-06-20
申请号：US164929
申请日：1998-10-01
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/223 , H01L21/265 , H01L21/28 , H01L21/306 , H01L21/3065 , H01L21/336 , H01L21/8234 , H01L29/04 , H01L29/423 , H01L29/51 , H01L29/94 , H01L29/08
CPC分类号： H01L21/28185 , H01L21/223 , H01L21/2652 , H01L21/28114 , H01L21/30608 , H01L21/3065 , H01L21/8234 , H01L29/045 , H01L29/42368 , H01L29/42376 , H01L29/66621 , H01L29/66636 , H01L29/78 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518
摘要： An integrated circuit and a method of making a transistor thereof are provided. The integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas. Each of the transistors has a gate dielectric layer with a V-shaped cross-section positioned on one of the plurality of active areas, a gate electrode positioned on the gate dielectric layer, a first source/drain region positioned in the substrate, and a second source/drain region positioned in the substrate in spaced-apart relation to the first source/drain region to define a channel region beneath the gate dielectric layer. The V-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate.
摘要翻译：提供集成电路及其制造晶体管的方法。集成电路包括基板和位于多个有效区域上的多个晶体管。每个晶体管具有位于多个有源区域中的一个上的V形截面的栅极电介质层，位于栅极电介质层上的栅极电极，位于衬底中的第一源极/漏极区域和第二源极/漏极区域以与第一源极/漏极区域间隔开的关系定位在衬底中，以限定栅极介电层下面的沟道区域。 V形栅极电介质层需要较少的水平衬底面积，使给定衬底具有更高的堆积密度。

28. 发明授权

US6005285A Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device 有权
标题翻译：用于抑制半导体器件内穿透的氩掺杂外延层
公开(公告)号：US6005285A
公开(公告)日：1999-12-21
申请号：US205321
申请日：1998-12-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/205 , H01L21/336 , H01L29/10 , H01L29/167 , H01L29/32 , H01L29/36
CPC分类号： H01L29/32 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L29/105 , H01L29/1079 , H01L29/167 , H01L29/66537 , H01L29/6659
摘要： A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a semiconductor substrate. In a preferred dual layer embodiment, a first argon doped silicon epilayer is grown over a substrate, and a second argon doped epilayer, preferably having an argon concentration less than that in the first epilayer, is formed over the first epilayer. A transistor is formed in an active region of a well having a channel laterally bounded by source/drain regions located exclusively in the second epilayer. The lighter argon doping of the second epilayer accommodates current flow in the channel while acting as a barrier to impurity outdiffusion and inhibiting punchthrough. The more heavily doped first epilayer serves primarily as a barrier to outdiffision of impurities from the bulk substrate.
摘要翻译：描述了制造工艺和晶体管，其中形成具有降低的穿透敏感性和增加的杂质扩散阻力的晶体管。在半导体衬底之上形成一个或多个氩掺杂硅外延层。在优选的双层实施例中，在衬底上生长第一氩掺杂硅外延层，并且在第一外延层上形成第二氩掺杂外延层，优选地具有比第一外延层中的氩浓度小的氩浓度。在阱的有源区中形成晶体管，该阱具有由专门位于第二外延层中的源极/漏极区横向限定的沟道。第二外延层的较轻的氩掺杂容纳通道中的电流，同时用作杂质向外扩散的屏障并抑制穿透。掺杂越多的第一外延层主要用作阻挡来自大块基板的杂质的障碍。

29. 发明授权

US5981363A Method and apparatus for high performance transistor devices 失效
标题翻译：高性能晶体管器件的方法和装置
公开(公告)号：US5981363A
公开(公告)日：1999-11-09
申请号：US193447
申请日：1998-11-17
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/51 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66659 , H01L21/2815 , H01L21/823425 , H01L21/823468 , H01L29/6656 , H01L29/7835 , H01L21/28194 , H01L21/28202 , H01L29/51 , H01L29/517 , H01L29/518 , Y10S438/947
摘要： The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a semiconducting substrate, and forming a layer of polysilicon above the layer of dielectric material. The method further comprises forming a layer of silicon nitride or silicon oxynitride above the layer of polysilicon, and patterning said layer of polysilicon and layer of silicon nitride or silicon oxynitride to define an opening and expose a sidewall surface of the polysilicon layer. The method continues with the growth of a lateral extension of the polysilicon layer and the oxidation of the extension. The method concludes with the patterning of the polysilicon layer to define a gate conductor, and the formation of source and drain regions in the substrate.
摘要翻译：本发明涉及一种形成具有减小的通道长度的半导体器件的方法。该方法包括在半导体衬底的表面上方形成电介质材料层，以及在介电材料层之上形成多晶硅层。该方法还包括在多晶硅层之上形成氮化硅或氮氧化硅层，以及图案化所述多晶硅层和氮化硅层或氮氧化硅层以限定开口并暴露多晶硅层的侧壁表面。该方法继续扩展多晶硅层的横向延伸和延伸的氧化。该方法结束于多晶硅层的图案化以限定栅极导体，以及在衬底中形成源极和漏极区域。

30. 发明授权

US06274442B1 Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same 失效
标题翻译：具有氮的外延生长栅电介质的晶体管及其制造方法
公开(公告)号：US06274442B1
公开(公告)日：2001-08-14
申请号：US09116417
申请日：1998-07-15
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably nitrogen atoms, within a barrier layer. The barrier layer is interposed between the gate dielectric and the semiconductor substrate. The barrier layer serves to inhibit the passage of dopants from the gate conductor into the channel area. The barrier layer is preferably a nitrogen doped silicon epitaxial layer. The barrier layer may be composed of two layers, a silicon epitaxial layer and a nitrogen doped epitaxial layer formed upon the silicon epitaxial layer.
摘要翻译：提供集成电路制造方法，用于在屏障层内并入屏障原子，优选氮原子。阻挡层介于栅电介质和半导体衬底之间。阻挡层用于抑制掺杂剂从栅极导体进入沟道区的过程。阻挡层优选为氮掺杂硅外延层。阻挡层可以由两层构成，硅外延层和形成在硅外延层上的氮掺杂外延层。

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