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21. 发明授权

US07030673B2 Phase splitter circuit 失效
公开(公告)号：US07030673B2
公开(公告)日：2006-04-18
申请号：US10197878
申请日：2002-07-19
申请人： Ki-Whan Song
发明人： Ki-Whan Song
IPC分类号： H03K11/26
CPC分类号： H03K5/151
摘要： A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.

22. 发明授权

US06580184B2 Electrostatic discharge (ESD) protection circuit of silicon-controlled rectifier (SCR) structure operable at a low trigger voltage 失效
标题翻译：可控硅整流器（SCR）结构的静电放电（ESD）保护电路可在低触发电压下工作
公开(公告)号：US06580184B2
公开(公告)日：2003-06-17
申请号：US10146046
申请日：2002-05-16
申请人： Ki-Whan Song
发明人： Ki-Whan Song
IPC分类号： H01L2974
CPC分类号： H01L27/0262 , Y10T307/74
摘要： An ESD protection circuit having silicon-controlled rectifier structure, includes a PNP transistor and an NPN transistor. A switch circuit is connected between a ground voltage terminal and a well region that is a base of the PNP transistor. The switch circuit is formed of plural diode-coupled MOS transistors, so that a trigger voltage of the SCR is determined by threshold voltages of the MOS transistors.
摘要翻译：具有硅控整流器结构的ESD保护电路包括PNP晶体管和NPN晶体管。开关电路连接在接地电压端子和作为PNP晶体管的基极的阱区域之间。开关电路由多个二极管耦合的MOS晶体管形成，从而SCR的触发电压由MOS晶体管的阈值电压决定。

23. 发明授权

US08772872B2 Transistors, semiconductor memory cells having a transistor and methods of forming the same 有权
标题翻译：晶体管，具有晶体管的半导体存储单元及其形成方法
公开(公告)号：US08772872B2
公开(公告)日：2014-07-08
申请号：US12588276
申请日：2009-10-09
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H01L27/12
CPC分类号： H01L29/7841 , H01L21/28114 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/41733 , H01L29/66553 , H01L29/7843 , H01L29/7846
摘要： Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.
摘要翻译：提供了具有晶体管的晶体管，具有晶体管的半导体存储单元及其形成方法，晶体管可以包括具有第一半导体区域的半导体衬底。栅极图案可以设置在第一半导体区域上。间隔图案可以各自设置在栅极图案的侧壁上。第二半导体区域和第三半导体区域可以设置在半导体衬底中。第二半导体区域可以设置在间隔图案下方。第三半导体区域可以被布置成与第二半导体区域相邻。第一半导体区域可以具有比第二半导体区域更高的杂质离子浓度。

24. 发明授权

US08503218B2 Nonvolatile memory device using resistance material and memory system including the nonvolatile memory device 有权
标题翻译：使用包括非易失性存储器件的电阻材料和存储器系统的非易失性存储器件
公开(公告)号：US08503218B2
公开(公告)日：2013-08-06
申请号：US13155492
申请日：2011-06-08
申请人： Jin-Young Kim , Ki-Whan Song
发明人： Jin-Young Kim , Ki-Whan Song
IPC分类号： G11C11/00 , G11C5/06 , G11C11/06 , G11C7/10
CPC分类号： G11C5/063 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038
摘要： A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.
摘要翻译：非易失性存储器件包括：存储器阵列，包括沿第一方向布置的多个存储体; 写入全局位线和在第一方向上延伸以由存储体共享的读取全局位线; 写入电路，连接到写入全局位线并且设置在存储器阵列的第一侧上; 以及读取电路，连接到读取的全局位线并且设置在与存储器阵列的第一侧相对的存储器阵列的第二侧上，其中每个存储体沿与第一方向不同的第二方向延伸并且包括多个的非易失性存储单元，每个非易失性存储单元具有可变电阻元件，其电阻值根据存储在其中的数据而变化。

25. 发明授权

US08134202B2 Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics 有权
标题翻译：具有改进的数据保存能力和操作特性的无电容的一晶体管半导体存储器件
公开(公告)号：US08134202B2
公开(公告)日：2012-03-13
申请号：US12453036
申请日：2009-04-28
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H01L29/792
CPC分类号： H01L29/7841 , H01L29/785
摘要： A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.
摘要翻译：提供其数据存储能力增加并且漏电流减小的无电容器一晶体管（1T）半导体器件。电容器1T半导体器件包括形成在基板上的掩埋绝缘层，形成在掩埋绝缘层上的有源区，并且包括源区域，漏极区域和形成在源极区域与漏极区域之间的浮体，以及形成在所述浮体上的栅极图案，其中，所述浮体包括具有与所述源极区域和所述漏极区域中的一个相同的顶部高度的主浮体，以及形成在所述主浮体和所述栅极之间的第一上浮体模式。

26. 发明授权

US08120979B2 Semiconductor memory devices having hierarchical bit-line structures 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US08120979B2
公开(公告)日：2012-02-21
申请号：US12591254
申请日：2009-11-13
申请人： Jin-Young Kim , Ki-Whan Song
发明人： Jin-Young Kim , Ki-Whan Song
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097 , G11C2207/002
摘要： The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation.
摘要翻译：半导体存储器件包括存储单元阵列和开关电路。存储单元阵列包括连接在字线和第一局部位线之间的多个第一存储单元，以及连接在字线和第二局部位线之间的多个第二存储单元。开关电路被配置为在第一感测周期期间将第一本地位线分别连接到第一全局位线，并且在读取操作的第二感测周期期间将第二局部位线分别连接到第二全局位线。半导体存储器件还包括感测电路，其被配置为在第一感测周期期间感测和放大来自第一全局位线的数据，并且在读取操作的第二感测周期期间感测和放大来自第二全局位线的数据。

27. 发明授权

US07777999B2 Electrostatic discharge (ESD) protection device 有权
标题翻译：静电放电（ESD）保护装置
公开(公告)号：US07777999B2
公开(公告)日：2010-08-17
申请号：US11969966
申请日：2008-01-07
申请人： Myoung-Gon Kang , Ki-Whan Song
发明人： Myoung-Gon Kang , Ki-Whan Song
IPC分类号： H02H9/00
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.
摘要翻译：静电放电（ESD）保护装置包括I / O端子结构和电流放电结构。电流放电结构包括通过栅极电极与桥接区域分离的导电区域，形成在导电区域下方的阱区域，通过另一导电区域与阱区域分离的另一阱区域以及实现双电流放电路径的多个附加导电区域通过另一个井区。

28. 发明授权

US07741673B2 Floating body memory and method of fabricating the same 失效
标题翻译：浮体记忆及其制造方法
公开(公告)号：US07741673B2
公开(公告)日：2010-06-22
申请号：US11853044
申请日：2007-09-11
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H01L29/788
CPC分类号： H01L27/10802 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A floating body memory includes a semiconductor substrate having a cell region and a peripheral circuit region. A floating body cell is located in the cell region and a first floating body is located in the peripheral circuit region of the semiconductor substrate. A peripheral gate pattern is positioned on the first floating body. First source and drain regions are positioned at both sides of the peripheral gate pattern. First leakage shielding patterns are positioned between the first floating body and the first source and drain regions, the first source and drain regions contacting the first floating body. The first leakage shielding patterns may be positioned outside outer edges of the peripheral gate pattern.
摘要翻译：浮体存储器包括具有单元区域和外围电路区域的半导体衬底。浮体单元位于单元区域中，并且第一浮体位于半导体基板的外围电路区域中。外围门图案位于第一浮体上。第一源极和漏极区域位于外围栅极图案的两侧。第一泄漏屏蔽图案位于第一浮体和第一源漏区之间，第一源区和漏区接触第一浮体。第一泄漏屏蔽图案可以位于外围栅极图案的外边缘外侧。

29. 发明申请

US20100149886A1 Semiconductor memory device and method for operating the same 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20100149886A1
公开(公告)日：2010-06-17
申请号：US12654283
申请日：2009-12-16
申请人： Ki-Whan Song , Nam-Kyun Tak
发明人： Ki-Whan Song , Nam-Kyun Tak
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation. Also, the controller is configured to restore data to the memory cell, which is storing a second data state, by applying a second source-line control voltage to the selected source line and applying a second word-line control voltage to the selected word line in a second period of the read operation.
摘要翻译：在示例实施例中，半导体存储器件以及用于操作半导体存储器件的方法包括具有多个存储单元的存储单元阵列，每个存储单元均由具有浮体的晶体管形成。晶体管耦合在多个字线，多条源极线和多个位线之间。此外，存储单元阵列包括控制器，其被配置为从存储器单元中的至少一个读取数据，并且通过存储器单元的位操作将数据恢复到存储第一数据状态的存储单元。控制器通过对所选择的源极线施加第一源极线控制电压并且在读取操作的第一周期中对所选择的字线施加第一字线控制电压来将数据恢复到存储器单元。此外，控制器被配置为通过对所选择的源极线施加第二源极线控制电压并将第二字线控制电压施加到所选择的字线来将数据恢复到存储第二数据状态的存储器单元在读操作的第二周期。

30. 发明申请

US20100090280A1 Transistors, semiconductor memory cells having a transistor and methods of forming the same 有权
标题翻译：晶体管，具有晶体管的半导体存储单元及其形成方法
公开(公告)号：US20100090280A1
公开(公告)日：2010-04-15
申请号：US12588276
申请日：2009-10-09
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H01L29/786
CPC分类号： H01L29/7841 , H01L21/28114 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/41733 , H01L29/66553 , H01L29/7843 , H01L29/7846
摘要： Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.
摘要翻译：提供了具有晶体管的晶体管，具有晶体管的半导体存储单元及其形成方法，晶体管可以包括具有第一半导体区域的半导体衬底。栅极图案可以设置在第一半导体区域上。间隔图案可以各自设置在栅极图案的侧壁上。第二半导体区域和第三半导体区域可以设置在半导体衬底中。第二半导体区域可以设置在间隔图案下方。第三半导体区域可以被布置成与第二半导体区域相邻。第一半导体区域可以具有比第二半导体区域更高的杂质离子浓度。

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