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21. 发明申请

US20120119685A1 POWER TRANSDUCER 有权
标题翻译：电力变压器
公开(公告)号：US20120119685A1
公开(公告)日：2012-05-17
申请号：US13357104
申请日：2012-01-24
申请人： Satoshi Ibori , Yoshihiro Uchino , Hiroshi Watanabe , Masahiro Hiraga
发明人： Satoshi Ibori , Yoshihiro Uchino , Hiroshi Watanabe , Masahiro Hiraga
IPC分类号： H02P3/12
CPC分类号： H02P3/22 , H02M1/32 , H02M5/458 , H02P3/14
摘要： The performance of a power transducer is improved while efficiently using a power semiconductor also by managing the permissible duty factor of the power semiconductor in the regenerative braking circuit provided in the power transducer. The user is allowed to set, through an operation panel provided on the power transducer, the resistance value of the regenerative braking resistor for thermally consuming the rotational energy generated during motor deceleration. The power transducer performs the steps of: calculating the current which flows in the regenerative braking circuit from the resistance value setting; obtaining the generation loss of the power semiconductor in the regenerative braking circuit with the calculated current value; and determining the permissible duty factor of the power semiconductor from the obtained generation loss.
摘要翻译：功率传感器的性能得到改善，同时通过管理设置在功率传感器中的再生制动电路中的功率半导体的允许占空比来有效地使用功率半导体。允许用户通过设置在功率传感器上的操作面板设置再生制动电阻器的电阻值，用于热消耗电动机减速期间产生的旋转能量。功率传感器执行以下步骤：从电阻值设定计算在再生制动电路中流动的电流; 以所计算的电流值获得再生制动电路中的功率半导体的发电损失; 以及从所获得的发电损失确定功率半导体的允许占空比。

22. 发明授权

US08174522B2 Three-dimensional (3D) structure data creation method, 3D structure data creation apparatus, computer-readable record media and computer system 有权
标题翻译：三维（3D）结构数据创建方法，3D结构数据创建装置，计算机可读记录介质和计算机系统
公开(公告)号：US08174522B2
公开(公告)日：2012-05-08
申请号：US12052198
申请日：2008-03-20
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： G06T15/00
CPC分类号： G06F17/50
摘要： A three-dimensional (3D) structure data creation technique capable of readily creating 3D structure data is disclosed. This method is for producing data of a 3D structure which is made up of a plurality of elements. The method includes the steps of preparing first and second two-dimensional (2D) sectional images different in normal vector from each other, forming first and second unit graphics based on these 2D images, partitioning each unit graphic on a per-element basis, performing layout arrangement of two unit graphics in accordance with normal vectors, expanding these unit graphics for conversion to 3D objects, and allocating a selected element to a region in which elements of the unit graphics failing to coincide with each other, which region is included in and specified from those regions with intersection of respective partitioned parts of the unit graphics, thereby to create the 3D structure data required.
摘要翻译：公开了能够容易地创建3D结构数据的三维（3D）结构数据创建技术。该方法用于生成由多个元素构成的3D结构的数据。该方法包括以下步骤：在法向量中彼此不同的第一和第二二维（2D）截面图像，基于这些2D图像形成第一和第二单位图形，基于每个元素划分每个单位图形，执行根据法向量布置两个单位图形的布局布置，将这些单位图形扩展到3D对象，并将所选择的元素分配到单元图形的元素彼此不一致的区域，该区域包括在哪个区域中，从具有相应的单位图形的分割部分的区域指定，从而创建所需的3D结构数据。

23. 发明授权

US08084802B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08084802B2
公开(公告)日：2011-12-27
申请号：US13025957
申请日：2011-02-11
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

24. 发明授权

US08039204B2 Manufacturing method of silicon carbide semiconductor apparatus 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08039204B2
公开(公告)日：2011-10-18
申请号：US12172453
申请日：2008-07-14
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： G03F7/26
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/1608 , H01L29/66068
摘要： A manufacturing method of a silicon carbide semiconductor apparatus is provided. The method includes forming a first resist pattern on a surface of a silicon carbide layer formed on a silicon carbide substrate, implanting a first conduction type impurity ion in the silicon carbide layer on which the first resist pattern is formed, forming a second resist pattern by decreasing a width of the first resist pattern with etching and forming a deposition layer on the surface of the silicon carbide layer which is not covered with the second resist pattern, and implanting a second conduction type impurity ion in the silicon carbide layer on which the second resist pattern is formed, through the deposition layer.
摘要翻译：提供了一种碳化硅半导体器件的制造方法。该方法包括在形成在碳化硅衬底上的碳化硅层的表面上形成第一抗蚀剂图案，在形成有第一抗蚀剂图案的碳化硅层中注入第一导电型杂质离子，通过通过蚀刻来减小第一抗蚀剂图案的宽度，并且在没有被第二抗蚀剂图案覆盖的碳化硅层的表面上形成沉积层，以及将第二导电型杂质离子注入到第二抗蚀剂图案的第二通过沉积层形成抗蚀剂图案。

25. 发明申请

US20110226541A1 Movable grille shutter for vehicle 有权
标题翻译：可移动格栅快门车
公开(公告)号：US20110226541A1
公开(公告)日：2011-09-22
申请号：US13064251
申请日：2011-03-14
申请人： Kenji Hori , Hiroshi Watanabe , Yoshimasa Asano , Masumi Nishikawa
发明人： Kenji Hori , Hiroshi Watanabe , Yoshimasa Asano , Masumi Nishikawa
IPC分类号： B60K11/08
CPC分类号： B60K11/085 , F01P7/10 , Y02T10/88
摘要： A movable grille shutter for a vehicle includes a fin adapted to be provided at a grille opening portion and being operated so as to freely open or close the grille opening portion through which ambient air is taken in, a drive source for driving the fin, a driving force transmitting mechanism for transmitting a driving force from the drive source to the fin and a flexible member being linked to the driving force transmitting mechanism and being deformed for operating the fin to open the grille opening portion in a case where a load that is equal to or more than a predetermined value is acted thereon.
摘要翻译：一种用于车辆的可移动格栅挡板包括：鳍片，其适于设置在格栅开口部分处并被操作以便自由地打开或关闭环境空气被引入的格栅开口部分，用于驱动翅片的驱动源，用于将驱动力从驱动源传递到翅片的驱动力传递机构，以及与驱动力传递机构连接并变形以在使负载相等的情况下变形以操作翅片以打开格栅开口部的柔性构件达到或大于预定值。

26. 发明授权

US08018194B2 Observation system and observation apparatus 有权
标题翻译：观察系统和观察装置
公开(公告)号：US08018194B2
公开(公告)日：2011-09-13
申请号：US12401044
申请日：2009-03-10
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： B64C17/06
CPC分类号： G02B21/24
摘要： When application software running on a PC is in the state of being terminated, a switch unit is turned OFF with the control of a CPU and individual motors, and in this state, a light source is not supplied with a motor/lamp-use power source. In this state, however, the CPU and individual I/Fs are supplied with a logic-use power source. Therefore, the switch unit is turned ON when the application software is started, and an initialization process for an individual electrically driven unit is no longer required.
摘要翻译：当在PC上运行的应用软件处于终止状态时，通过CPU和单独的电动机的控制将开关单元关闭，并且在该状态下，不向光源提供电动机/灯用电力资源。然而，在这种状态下，CPU和各个I / F被提供有逻辑电源。因此，当应用软件启动时，开关单元被接通，并且不再需要用于单独的电驱动单元的初始化处理。

27. 发明申请

US20110189503A1 SURFACE-TREATED COPPER FOIL 有权
标题翻译：表面处理铜箔
公开(公告)号：US20110189503A1
公开(公告)日：2011-08-04
申请号：US13002394
申请日：2009-06-26
申请人： Seiji Nagatani , Hiroshi Watanabe , Kazufumi Izumida
发明人： Seiji Nagatani , Hiroshi Watanabe , Kazufumi Izumida
IPC分类号： B32B15/04
CPC分类号： H05K3/382 , B32B15/08 , B32B15/20 , B32B27/06 , B32B2255/06 , B32B2255/20 , B32B2255/26 , B32B2255/28 , B32B2307/206 , B32B2307/50 , B32B2307/538 , B32B2307/714 , B32B2307/732 , B32B2307/75 , C23C14/024 , C23C14/14 , H05K3/388 , H05K2201/0179 , H05K2201/0317 , H05K2201/0323 , Y10T428/12028 , Y10T428/12438 , Y10T428/12625 , Y10T428/12681 , Y10T428/12806 , Y10T428/12903 , Y10T428/24975 , Y10T428/265
摘要： Object is to provide a surface-treated copper foil free from chromium in the surface-treatment layer and excellent in peel strength of a circuit and chemical resistance against to degradation of the peel strength after processing into a printed wiring board. To achieve the object, the surface-treated copper foil having a surface-treatment layer on a bonding surface of a copper foil for manufacturing a copper-clad laminate by laminating it to an insulating resin substrate has the surface-treatment layer formed by depositing a metal component having high melting point not lower than 1400° C. by dry process film formation method to the bonding surface of the copper foil after the cleaning treatment and further depositing a carbon component to the surface.
摘要翻译：本发明提供一种在表面处理层中不含铬的表面处理铜箔，并且电路的剥离强度优异，并且在加工成印刷线路板之后，耐化学性能降低剥离强度。为了实现该目的，在覆铜层压板的制造用铜箔的接合面上具有表面处理层的表面处理铜箔通过层叠在绝缘性树脂基板上而形成有表面处理层，通过干法成膜法将熔点不低于1400℃的高熔点金属成分施加到清洁处理后的铜箔的接合面上，并进一步在表面上沉积碳成分。

28. 发明申请

US20110134700A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110134700A1
公开(公告)日：2011-06-09
申请号：US13025957
申请日：2011-02-11
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

29. 发明授权

US07939020B2 Automatic analyzing apparatus 有权
标题翻译：自动分析仪
公开(公告)号：US07939020B2
公开(公告)日：2011-05-10
申请号：US11797240
申请日：2007-05-02
申请人： Keiko Nogawa , Michiaki Sekiguchi , Hiroshi Watanabe , Hiroaki Ishizawa , Terumi Tamura
发明人： Keiko Nogawa , Michiaki Sekiguchi , Hiroshi Watanabe , Hiroaki Ishizawa , Terumi Tamura
IPC分类号： G01N21/00 , G01N31/00 , G01N35/02
CPC分类号： G01N35/026 , G01N2035/0415 , G01N2035/0472 , Y10T436/11 , Y10T436/110833 , Y10T436/113332 , Y10T436/114165 , Y10T436/115831
摘要： An automatic analyzing apparatus has an analysis section including an immunity analysis unit and a biochemical componential analysis unit. A sample rack which has undergone the immunity componential analysis is horizontally fed by a rack feeding mechanism from a position confronting the inlet of a rack stationing section to a position near the outlet of the rack stationing section, so that the sample rack is directly moved to a return line, while skipping over the rack stationing section, so as to be efficiently returned to the analysis section and subjected to a subsequent biochemical analysis. A sample rack that needs reexamination by an identical analysis unit is also returned in the same efficient way.
摘要翻译：自动分析装置具有包括免疫分析单元和生化分析单元的分析部。已经经过免疫组分分析的样品架通过齿条进给机构从面向机架定位部分的入口的位置到靠近机架定位部分出口处的位置水平馈送，使样品架直接移动到返回线，同时跳过机架驻留部分，以便有效地返回到分析部分并进行随后的生化分析。需要通过相同分析单元进行复检的样品架也以相同的有效方式返回。

30. 发明申请

US20110001209A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110001209A1
公开(公告)日：2011-01-06
申请号：US12867283
申请日：2009-03-12
申请人： Hiroshi Watanabe , Naoki Yutani , Kenichi Ohtsuka , Kenichi Kuroda , Masayuki Imaizumi , Yoshinori Matsuno
发明人： Hiroshi Watanabe , Naoki Yutani , Kenichi Ohtsuka , Kenichi Kuroda , Masayuki Imaizumi , Yoshinori Matsuno
IPC分类号： H01L29/47
CPC分类号： H01L29/872 , H01L21/0495 , H01L24/05 , H01L29/0619 , H01L29/1608 , H01L29/6606 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− typesemiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.
摘要翻译：在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成由形成在所述GR层之外的围绕所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。

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