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21. 发明授权

US07687368B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07687368B2
公开(公告)日：2010-03-30
申请号：US11088885
申请日：2005-03-25
申请人： Hirohisa Kawasaki , Kazunari Ishimaru , Kunihiro Kasai , Yasunori Okayama
发明人： Hirohisa Kawasaki , Kazunari Ishimaru , Kunihiro Kasai , Yasunori Okayama
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76208 , H01L21/823807 , H01L21/823878
摘要： A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.
摘要翻译：公开了半导体器件制造方法。该方法是形成与第一半导体层上的第一半导体层相比具有比绝缘特性更小的敏感性的第二半导体层。然后，露出第二和第一半导体层的部分的槽形成为从第二半导体层的上表面延伸到第一半导体层。接下来，暴露于凹槽的第一和第二半导体层的部分被改变为绝缘体形式，以用第一半导体层的绝缘体形式部分填充沟槽。

22. 发明申请

US20070164364A1 SEMICONDUCTOR DEVICE USING SIGE FOR SUBSTRATE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：使用基板的信号的半导体器件及其制造方法
公开(公告)号：US20070164364A1
公开(公告)日：2007-07-19
申请号：US11619799
申请日：2007-01-04
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L29/94
CPC分类号： H01L29/1054 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.
摘要翻译：半导体器件包括第一半导体层，n型/ p型第二半导体层，p型/ n型第三半导体层和第一栅电极。第二半导体层形成在第一半导体层上，其氧化速率低于第一半导体层的氧化速率。第三半导体层形成在第二半导体层中，并且具有到达第一半导体层的内部的深度。在第二和第三半导体层分别为n型和p型的情况下，第二半导体层的晶格常数小于第三半导体层的晶格常数。在第二和第三半导体层分别为p型和n型的情况下，第二半导体层的晶格常数大于第三半导体层的晶格常数。在第二半导体层上形成第一栅电极。

23. 发明申请

US20050133819A1 Semiconductor device using strained silicon layer and method of manufacturing the same 审中-公开
标题翻译：使用应变硅层的半导体器件及其制造方法
公开(公告)号：US20050133819A1
公开(公告)日：2005-06-23
申请号：US10972001
申请日：2004-10-25
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/786 , H01L29/10
CPC分类号： H01L21/823807
摘要： A semiconductor device includes a substrate-strained Si formed of a first semiconductor layer which has a first lattice constant and formed on a semiconductor substrate, and a second semiconductor layer which has a second lattice constant and epitaxially grows such that a lattice of the second semiconductor layer matches that of the first semiconductor layer. The semiconductor device further includes a first conductive type metal oxide semiconductor (MOS) transistor which is formed in a first region on the substrate-strained Si and has the second semiconductor layer modified so as to have a first thickness, and a second conductive type MOS transistor which is formed in a second region on the substrate-strained Si and has the second semiconductor layer modified-so as to have a second thickness thinner than the first thickness.
摘要翻译：半导体器件包括由半导体衬底上形成的第一晶格常数的第一半导体层形成的衬底应变Si和具有第二晶格常数并且外延生长的第二半导体层，使得第二半导体层与第一半导体层的匹配。半导体器件还包括第一导电型金属氧化物半导体（MOS）晶体管，该第一导电型金属氧化物半导体（MOS）晶体管形成在基板应变Si上的第一区域中，并且具有被修改为具有第一厚度的第二半导体层，以及第二导电型MOS 晶体管，其形成在衬底应变Si上的第二区域中，并且具有被修改的第二半导体层，以具有比第一厚度更薄的第二厚度。

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