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21. 发明授权

US07064375B2 Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof 失效
标题翻译：具有栅电极和扩散层的半导体存储器件及其制造方法
公开(公告)号：US07064375B2
公开(公告)日：2006-06-20
申请号：US10602595
申请日：2003-06-25
申请人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
发明人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.
摘要翻译：一种半导体存储器件，包括具有第一栅电极，第一扩散层和第二扩散层的第一存储单元; 连接到第一存储单元的第一扩散层的第一接触层; 连接到所述第一接触层的第二接触层; 第二存储单元，具有第二栅电极，第三扩散层和第四扩散层，第二存储单元的第二栅电极与第一存储单元的第一栅极电连接，第一和第二存储单元布置在垂直于第一位线的方向; 以及与第一存储单元的第二扩散层和第二存储单元的第四扩散层共同连接的导电层，导电层的高度与第一接触层的高度基本上共面。

22. 发明授权

US06828621B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06828621B2
公开(公告)日：2004-12-07
申请号：US10679431
申请日：2003-10-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

23. 发明授权

US06803623B2 Nonvolatile semiconductor memory device which can operate at high speed with low voltage, and manufacturing method there 失效
标题翻译：可以低电压高速运行的非易失性半导体存储器件，以及制造方法
公开(公告)号：US06803623B2
公开(公告)日：2004-10-12
申请号：US10003434
申请日：2001-12-06
申请人： Nobuyo Sugiyama , Shinji Odanaka , Hiromasa Fujimoto , Seiki Ogura
发明人： Nobuyo Sugiyama , Shinji Odanaka , Hiromasa Fujimoto , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： The nonvolatile semiconductor memory device has a floating gate electrode that is formed on the semiconductor region and stores carriers injected from the semiconductor region and a control gate electrode that controls the quantity of stored carriers by applying a predetermined voltage to the floating gate electrode. The source region is formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode, while the drain region is formed on the other of the side regions thereof. The drain region creates an electric field from which the carriers injected into the floating gate electrode are subject to an external force having an element directed from the semiconductor region to the floating gate electrode.
摘要翻译：非易失性半导体存储器件具有形成在半导体区域上并存储从半导体区域注入的载流子的浮置栅电极和通过向浮置栅电极施加预定电压来控制存储载流量的控制栅电极。源极区域形成在浮置栅极电极和控制栅电极的一个侧区域的半导体区域中，而漏极区域形成在另一个侧面区域上。漏极区域产生电场，从该电场注入到浮栅中的载流子受到具有从半导体区域指向浮栅的元件的外力。

24. 发明授权

US06642572B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06642572B2
公开(公告)日：2003-11-04
申请号：US10382520
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

25. 发明授权

US06538275B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06538275B2
公开(公告)日：2003-03-25
申请号：US09902942
申请日：2001-07-12
申请人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
发明人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween. Within the semiconductor substrate and in the vicinity of the stepped portion, there is formed a depletion control layer which is composed of a heavily doped impurity region and formed to extend from a position located under the floating gate electrode and at a distance from the upper corner of the stepped portion toward the lower corner of the stepped portion and adjoin the end portion of a drain region without reaching a step side region.

26. 发明授权

US5227323A Method of manufacturing capacitor elements in an integrated circuit having a compound semiconductor substrate 失效
标题翻译：在具有化合物半导体衬底的集成电路中制造电容器元件的方法
公开(公告)号：US5227323A
公开(公告)日：1993-07-13
申请号：US901296
申请日：1992-06-19
申请人： Mitsuru Nishitsuji , Hiromasa Fujimoto
发明人： Mitsuru Nishitsuji , Hiromasa Fujimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8252 , H01L27/06
CPC分类号： H01L21/8252 , H01L27/0605
摘要： A capacitor element is formed in an integrated circuit having a compound semiconductor substrate such as a GaAs substrate and having Schottky type FETs formed on the substrate, with the capacitor element being formed by a process in which a lower electrode of a capacitor element and a lower layer portion of the gate electrode of a FET are formed by the same processing step from a high melting-point tungsten compound, a film of insulating material having a high dielectric coefficient is formed overall and is patterned to expose the gate electrode lower layer, and a high-conductance metallic film is then deposited overall and patterned to form an upper electrode of the capacitor element and an upper layer portion of the gate electrode. Capacitor elements and FETs can thereby be formed in such an IC by a simple process, while substantial reduction of the substrate area occupied by each capacitor element can be achieved.
摘要翻译：电容器元件形成在具有诸如GaAs衬底的化合物半导体衬底和形成在衬底上的肖特基型FET的集成电路中，电容器元件通过以下工艺形成，其中电容器元件的下电极和下电极通过与高熔点钨化合物相同的处理步骤形成FET的栅电极的层部分，整体形成具有高介电系数的绝缘材料的膜，并对其进行构图以露出栅电极下层，以及然后将高电导金属膜整体沉积并图案化以形成电容器元件的上电极和栅电极的上层部分。因此，可以通过简单的工艺在这种IC中形成电容器元件和FET，同时可以实现每个电容器元件占据的基板面积的显着减小。

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