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21. 发明申请

US20080213231A1 Pluripotent Stem Cell Cloned From Single Cell Derived From Skeletal Muscle Tissue 审中-公开
标题翻译：来自骨骼肌组织的单细胞克隆的多能干细胞
公开(公告)号：US20080213231A1
公开(公告)日：2008-09-04
申请号：US11988836
申请日：2006-07-14
申请人： Hidemasa Oh , Tetsuya Nomura , Hiroaki Matsubara
发明人： Hidemasa Oh , Tetsuya Nomura , Hiroaki Matsubara
IPC分类号： A61K35/12 , C12N5/06 , C12Q1/02 , A61P9/00
CPC分类号： A61K35/545 , A61K35/34 , C12N5/0657 , C12N5/0668 , C12N2502/1335 , G01N33/5073
摘要： Techniques are provided which can isolate pluripotent stem cells at high purity capable of differentiation into at least a myocardial cell to regenerate the cardiac muscle. The pluripotent stem cells at high purity capable of differentiation into at least a myocardial cell to regenerate the cardiac muscle can be isolated through the following steps: (i) collecting a skeletal muscle tissue from a mammal and enzymatically treating the obtained skeletal muscle tissue to prepare a skeletal muscle tissue-derived cell; (ii) culturing the obtained skeletal muscle tissue-derived cell in a culture medium containing an epidermal growth factor and a fibroblast growth factor; (iii) selecting and separating a colony that is floating in the culture medium.
摘要翻译：提供了能够将能够分化为至少心肌细胞的高纯度的多能干细胞分离以再生心肌的技术。可以通过以下步骤分离能够分化为至少心肌细胞以再生心肌的高纯度的多能干细胞：（i）从哺乳动物收集骨骼肌组织并酶处理所获得的骨骼肌组织以制备骨骼肌组织来源的细胞; （ii）在含有表皮生长因子和成纤维细胞生长因子的培养基中培养得到的骨骼肌组织来源的细胞; （iii）选择和分离在培养基中漂浮的菌落。

22. 发明授权

US5224072A Read-only memory with few programming signal lines 失效
标题翻译：只读存储器，编程信号线很少
公开(公告)号：US5224072A
公开(公告)日：1993-06-29
申请号：US680329
申请日：1991-04-04
申请人： Hiroaki Matsubara
发明人： Hiroaki Matsubara
IPC分类号： G11C7/22 , G11C16/32
CPC分类号： G11C7/22 , G11C16/32
摘要： A signal-generating circuit receives a program signal and generates an output enable signal, a control signal, and a latch signal. In response to the output enable signal, a programmable read-only memory outputs data onto a data bus. In response to the control signal, a three-state buffer outputs data from a first register to the data bus; the data can then be stored in the programmable read-only memory by input of a chip enable signal. In response to the latch signal, a second register latches data output from the programmable read-only memory onto the data bus. An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether they are equal.
摘要翻译：信号发生电路接收编程信号并产生输出使能信号，控制信号和锁存信号。响应于输出使能信号，可编程只读存储器将数据输出到数据总线上。响应于控制信号，三态缓冲器将数据从第一寄存器输出到数据总线; 然后可以通过输入芯片使能信号将数据存储在可编程只读存储器中。响应于锁存信号，第二寄存器将从可编程只读存储器输出的数据锁存到数据总线上。相等检验器比较第一和第二寄存器的内容，并产生指示它们是否相等的相等的信号。

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