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21. 发明申请

US20070011406A1 Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries 有权
标题翻译：通过禁止使用有缺陷的高速缓存条目来增加具有高速缓冲存储器的装置的产量的系统和方法
公开(公告)号：US20070011406A1
公开(公告)日：2007-01-11
申请号：US11175504
申请日：2005-07-06
申请人： Satoru Takase , Yasuhiko Kurosawa
发明人： Satoru Takase , Yasuhiko Kurosawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/1027
摘要： Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a cache replacement manager determines in which of n possible entries data will be replaced. The cache replacement manager is configured to take into account whether each cache entry is defective when determining whether to select that entry as the destination entry for new data. The cache manager unit may implement a least-recently-used policy in selecting the cache entry in which the new data will be replaced. The cache replacement manager then treats any defective entries as if they hold the most recently used data, and thereby avoids selecting defective entries as the destination for new data. In one embodiment, the cache performs index translation before indexing into each set of cache entries in order to effectively redistribute defective entries among the indices.
摘要翻译：通过选择性地避免使用包括缺陷的缓存条目来增加结合集相关高速缓冲存储器的装置的产量的系统和方法。在一个实施例中，高速缓存替换管理器确定n个可能条目中的哪一个将被替换。高速缓存替换管理器被配置为在确定是否选择该条目作为新数据的目的地条目时考虑每个高速缓存条目是否有缺陷。高速缓存管理器单元可以在选择其中新数据将被替换的高速缓存条目中实现最近最少使用的策略。然后，高速缓存替换管理器将任何缺陷条目视为保持最近使用的数据，从而避免选择有缺陷的条目作为新数据的目的地。在一个实施例中，高速缓存在索引到每组高速缓存条目之前执行索引转换，以便有效地重新分配索引中的缺陷条目。

22. 发明授权

US06188618B1 Semiconductor device with flexible redundancy system 失效
标题翻译：具有灵活冗余系统的半导体器件
公开(公告)号：US06188618B1
公开(公告)日：2001-02-13
申请号：US09296269
申请日：1999-04-22
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812
摘要： A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.
摘要翻译：存储单元阵列包括用于保存有缺陷单元的备用元件。熔丝组每个都包含有缺陷的地址和指示熔丝组与备用元件之间的关系的映射信息。当缺陷地址与输入地址相匹配时，每个保险丝组输出用于激活相应备用元件的信号。芯片内的熔丝组数量小于备用元件的数量。

23. 发明授权

US5586078A Dynamic type memory 失效
标题翻译：动态类型内存
公开(公告)号：US5586078A
公开(公告)日：1996-12-17
申请号：US528306
申请日：1995-09-14
申请人： Satoru Takase , Kiyofumi Sakurai , Masaki Ogihara
发明人： Satoru Takase , Kiyofumi Sakurai , Masaki Ogihara
IPC分类号： G11C11/401 , G06F12/08 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/4091 , G11C11/4096
摘要： A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.
摘要翻译： DRAM包括以共享读出放大器配置划分的形式的存储器块，其中用作高速缓冲存储器的子阵列和读出放大器在存储器芯片的X方向上交替排列。存储块沿Y方向排列。数据线与对应的子阵列的Y方向平行地形成，用于传送保持在与子阵列相对应的读出放大器中的数据。 I / O焊盘与X方向平行布置，用于经由数据线向/从相应的子阵列输入/输出数据。当在DRAM的小区域中实现共享读出放大器配置和读出放大器缓存系统时，高速缓冲存储器的命中率增加，并且可以通过缩短存储芯片中形成的数据路径来高速传输数据。

24. 发明授权

US08207613B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08207613B2
公开(公告)日：2012-06-26
申请号：US12718374
申请日：2010-03-05
申请人： Yuki Okukawa , Satoru Takase
发明人： Yuki Okukawa , Satoru Takase
IPC分类号： H01L23/48
CPC分类号： H01L27/101 , H01L27/222 , H01L27/24
摘要： A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.
摘要翻译：一种半导体存储器件，包括：一个包括彼此交叉的第一和第二布线的单元阵列层; 形成在所述电池阵列层下方的第一布线层上的第三布线; 形成在所述电池阵列层上方的第二布线层上的第四布线; 以及在堆叠方向上延伸的用于连接第三和第四布线的接触件，其中所述装置还包括在所述第一和第二布线层之间形成的冗余布线层，所述冗余布线层形成有冗余布线，所述冗余布线具有部分沿与第三和第四布线，第三布线和第三布线以及第三布线和第四布线中的至少一个相同的方向延伸，并且第四布线和冗余布线通过沿与沿着相同方向延伸的部分布置的多个触点连接第三或第四布线。

25. 发明授权

US07978499B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07978499B2
公开(公告)日：2011-07-12
申请号：US12556272
申请日：2009-09-09
申请人： Koji Hosono , Satoru Takase
发明人： Koji Hosono , Satoru Takase
IPC分类号： G04B25/02 , G04B27/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2213/71 , G11C2213/72
摘要： A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit configured to output a first signal based on a first current flowing through a selected memory cell and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time. The signal output circuit is configured to determine the first current based on the second current retained by the current retaining circuit. The control circuit is configured to stop application of the first voltage to the first wirings based on the first signal.
摘要翻译：半导体存储装置包括：具有存储单元的存储单元阵列; 以及控制电路，被配置为将第一电压施加到所选择的第一布线中的一个，以及将第二电压施加到所选择的第二布线中的一个。控制电路包括：信号输出电路，被配置为基于流过所选择的存储单元的第一电流和参考电流来输出第一信号; 以及电流保持电路，其被配置为在一定时间段期间保持流过所述第一布线的第二电流或电连接到所述第一布线的布线。信号输出电路被配置为基于由电流保持电路保持的第二电流来确定第一电流。控制电路被配置为基于第一信号停止将第一电压施加到第一布线。

26. 发明申请

US20080112236A1 Systems and Methods for Improving Memory Reliability by Selectively Enabling Word Line Signals 有权
标题翻译：通过选择性地启用字线信号来提高存储器可靠性的系统和方法
公开(公告)号：US20080112236A1
公开(公告)日：2008-05-15
申请号：US11558045
申请日：2006-11-09
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08 , G11C11/417
摘要： Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.
摘要翻译：用于通过禁止当电压不在可接受的范围内访问存储器单元的字线信号的断言来减少存储器单元电压（Vcell）和逻辑电压（Vdd）之间相对变化引起的不稳定性和可编写性问题的系统和方法工作范围。一个实施例包括具有临界状态检测器的系统，其被配置为监视电压并确定电压是否在可接受的范围内。当电压不在可接受范围内时，系统禁止对存储单元的字线断言。当导致信号被禁止的关键条件不再存在时，由存储器控制器重试由于禁止字线信号而失败的存储器访问。

27. 发明申请

US20080062747A1 Systems and methods for improving memory reliability 失效
标题翻译：提高内存可靠性的系统和方法
公开(公告)号：US20080062747A1
公开(公告)日：2008-03-13
申请号：US11530271
申请日：2006-09-08
申请人： Satoru Takase , Takehito Sasaki
发明人： Satoru Takase , Takehito Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C5/143 , G11C5/147
摘要： Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.
摘要翻译：用于减少由电压之间的相对变化引起的不稳定性和可编写性问题的系统和方法，其中存储单元和访问存储器单元的逻辑组件通过在电压不在可接受的工作范围内时禁止存储器访问而工作。一个实施例包括流水线处理器，其具有在第一电压处接收功率的逻辑部件和以第二电压接收功率的一组SRAM单元。临界条件检测器被配置为监视第一和第二电压并且确定这些电压的比率是否在可接受的范围内。当电压不在可接受范围内时，产生异常，异常处理程序使处理器流水线停止以禁止对SRAM单元的访问。当电压返回到可接受的范围时，异常处理程序将恢复流水线并完成异常的处理。

28. 发明申请

US20070297256A1 Systems and Methods for Data Transfers Between Memory Cells 有权
标题翻译：记忆单元之间数据传输的系统和方法
公开(公告)号：US20070297256A1
公开(公告)日：2007-12-27
申请号：US11425438
申请日：2006-06-21
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/02
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/065 , G11C11/4091 , G11C11/4093
摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.
摘要翻译：通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。每个读出放大器被配置为选择性地耦合到数据线。在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器，第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

29. 发明申请

US20060267691A1 System and method for phase-locked loop leak compensation 失效
标题翻译：锁相环泄漏补偿系统及方法
公开(公告)号：US20060267691A1
公开(公告)日：2006-11-30
申请号：US11136817
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/18
摘要： Phased-lock loop (PLL) system and method for compensating current leakage where current leakage may include gate-leak current attributable to a gate capacitor. In particular, providing a compensation current to an input node of a voltage-controlled oscillator (VCO) to substantially compensate current leakage and therefore reduce PLL jitter. The PLL circuit includes a compensation charge pump which receives input from a counter and in turn provides a counter-value-proportional compensation current. The counter value increments and decrements according to up and down inputs from a phase frequency detector. The counter value is fixed when the PLL circuit is locked. The PLL circuit is driven to lock by the compensation charge pump, with or without the aid of another charge pump. While the PLL is locked, the compensation charge pump may provide a fixed counter-value-proportional compensation current.
摘要翻译：用于补偿电流泄漏的相位锁定环路（PLL）系统和方法，其中电流泄漏可能包括归属于栅极电容器的栅极漏电流。特别地，向压控振荡器（VCO）的输入节点提供补偿电流，以基本上补偿电流泄漏并因此降低PLL抖动。 PLL电路包括补偿电荷泵，其接收来自计数器的输入，并且进而提供反值比例补偿电流。计数器值根据相位频率检测器的上下输入递增和递减。 PLL电路锁定时，计数器值固定。驱动PLL电路由补偿电荷泵锁定，无论是否使用另一个电荷泵。当PLL被锁定时，补偿电荷泵可以提供固定的反值比例补偿电流。

30. 发明申请

US20060267642A1 System and method for lock detection of a phase-locked loop circuit 失效
标题翻译：锁相环电路锁定检测系统及方法
公开(公告)号：US20060267642A1
公开(公告)日：2006-11-30
申请号：US11137072
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/089 , H03L7/0895 , H03L2207/14 , Y10S331/02
摘要： Systems and methods for detecting phase-locked loop circuit lock. In particular, a lock detector configured to detect PLL stability for a user-defined period of time prior to asserting a PLL-lock-detected output. Stability may be indicated by a counter inserted into a PLL circuit and arranged between a phase-frequency detector and a charge pump. Because the counter value is acted upon by the phase-frequency detector, PLL lock is indicated by counter value stability. The digital counter value may be provided to a digital charge pump and a lock detector simultaneously. The lock detector includes registers and difference detectors to determine when the difference between counter values is below a user-defined tolerance. The lock detector may include a variable timer to avoid false indications of lock which may occur when counter values are sampled with the same frequency as a fluctuation frequency of the counter value.
摘要翻译：用于检测锁相环电路锁的系统和方法。特别地，锁定检测器被配置为在断言PLL锁定检测到的输出之前检测用户定义的时间段的PLL稳定性。稳定性可以由插入PLL电路中的计数器指示并且布置在相位频率检测器和电荷泵之间。由于计数器值由相位频率检测器作用，PLL锁定由计数器值稳定性指示。数字计数器值可以同时提供给数字电荷泵和锁定检测器。锁定检测器包括寄存器和差分检测器，用于确定计数器值之间的差异何时低于用户定义的公差。锁定检测器可以包括可变定时器，以避免在以与计数器值的波动频率相同的频率对计数器值进行采样时可能发生的锁定的错误指示。

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