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21. 发明授权

US06448127B1 Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets 有权
标题翻译：用于在高k /氧化物堆叠栅极电介质中形成超薄基础氧化物的工艺
公开(公告)号：US06448127B1
公开(公告)日：2002-09-10
申请号：US09740606
申请日：2000-12-19
申请人： Qi Xiang , Joong Jeon , Colman Wong
发明人： Qi Xiang , Joong Jeon , Colman Wong
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28238 , H01L21/823857 , H01L29/513 , H01L29/518 , Y10S438/976 , Y10S438/981
摘要： A method and article of manufacture of an ultra-thin base oxide or nitrided oxide layer in a CMOS device. The method and article of manufacture are formed by providing a silicon wafer with an initial oxide layer which is removed from the silicon wafer by a hydrogen baking step. A new oxide layer or nitrided oxide layer is formed by thermal growth on the silicon wafer surface. A portion of the new oxide layer is removed by hydrogen annealing. A MOSFET can be created by forming a gate electrode structure on a high-k dielectric material deposited on the new oxide layer.
摘要翻译：在CMOS器件中的超薄基底氧化物或氮化氧化物层的制造方法和制造方法。该方法和制造方法通过提供硅晶片来形成，该初始氧化物层通过氢焙烧步骤从硅晶片上除去。通过在硅晶片表面上的热生长形成新的氧化物层或氮化氧化物层。通过氢退火除去一部分新的氧化物层。可以通过在沉积在新氧化物层上的高k电介质材料上形成栅电极结构来产生MOSFET。

22. 发明授权

US06187657B1 Dual material gate MOSFET technique 失效
标题翻译：双材料栅极MOSFET技术
公开(公告)号：US06187657B1
公开(公告)日：2001-02-13
申请号：US09275486
申请日：1999-03-24
申请人： Qi Xiang , Joong Jeon
发明人： Qi Xiang , Joong Jeon
IPC分类号： H01L2128
CPC分类号： H01L21/28202 , H01L21/28105 , H01L21/31111 , H01L21/823842 , H01L29/4983 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： This invention comprises a new technique to realize a dual material gate MOSFET. The inventive technique is base upon an asymmetric oxide spacer formation and a self-aligned silicide formation. The asymmetric oxide spacer on the sidewall of the drain side of the gate is formed by selectively etching the spacer on the source side. The etch selectivity is realized by nitrogen implantation into an oxide spacer on the source side, by utilizing preferably an angled ion implantation technique. An HF solution has been experimentally demonstrated to provide an etch rate of the nitrogen implanted oxide that is much faster than the oxide without the nitrogen implantation.
摘要翻译：本发明包括实现双材料栅极MOSFET的新技术。本发明的技术基于不对称氧化物间隔物形成和自对准硅化物形成。通过选择性地蚀刻源极侧的间隔物来形成栅极的漏极侧的侧壁上的非对称氧化物间隔物。通过优选采用成角度的离子注入技术，通过将氮注入到源极上的氧化物隔离物中来实现蚀刻选择性。实验证明，HF溶液提供氮注入氧化物的蚀刻速率，其比没有氮注入的氧化物要快得多。

23. 发明授权

US07468296B1 Thin film germanium diode with low reverse breakdown 有权
标题翻译：薄膜锗二极管具有低反向击穿功能
公开(公告)号：US07468296B1
公开(公告)日：2008-12-23
申请号：US11290787
申请日：2005-11-30
申请人： Ercan Adem , Matthew Buynoski , Robert Chiu , Bryan Choo , Calvin Gabriel , Joong Jeon , David Matsumoto , Jeffrey Shields , Bhanwar Singh , Winny Stockwell , Wen Yu
发明人： Ercan Adem , Matthew Buynoski , Robert Chiu , Bryan Choo , Calvin Gabriel , Joong Jeon , David Matsumoto , Jeffrey Shields , Bhanwar Singh , Winny Stockwell , Wen Yu
IPC分类号： H01L21/8234 , H01L27/10
CPC分类号： H01L27/1021
摘要： In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.
摘要翻译：在制造电子结构时，提供基板，并且在基板上设置第一阻挡层。锗薄膜二极管设置在第一阻挡层上，第二阻挡层设置在锗薄膜二极管上。存储器件设置在第二阻挡层上并连接到第二阻挡层。

24. 发明申请

US20080149986A1 ZERO INTERFACE POLYSILICON TO POLYSILICON GATE FOR FLASH MEMORY 有权
标题翻译：零界面多晶硅用于闪存存储器的多晶硅栅极
公开(公告)号：US20080149986A1
公开(公告)日：2008-06-26
申请号：US11614801
申请日：2006-12-21
申请人： Robert Bertram Ogle, Jr. , Joong Jeon , Austin Frenkel , Eric Paton
发明人： Robert Bertram Ogle, Jr. , Joong Jeon , Austin Frenkel , Eric Paton
IPC分类号： H01L21/4763 , H01L29/788 , B05C11/02
CPC分类号： H01L21/28273 , H01L21/02068 , H01L27/11526 , H01L27/11531
摘要： A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.
摘要翻译：公开了一种用于处理闪存器件的零氧化物界面双重多晶硅结构的系统和方法。示例性的方法可以包括去除第一多晶硅层的表面上的氧化物并在同一处理室中在第一多晶硅层上形成第二多晶硅层。不需要从氧化物去除工具到例如多层形成工具，植入工具等的结构的转移。结果，在第一和第二多层的界面处不形成含有由第一多晶硅层暴露于含氧气氛的氧化硅的杂质。

25. 发明授权

US06562491B1 Preparation of composite high-K dielectrics 有权
标题翻译：复合高K电介质的制备
公开(公告)号：US06562491B1
公开(公告)日：2003-05-13
申请号：US09977922
申请日：2001-10-15
申请人： Joong Jeon
发明人： Joong Jeon
IPC分类号： B32B1504
CPC分类号： H01L21/28185 , H01L21/28194 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device and a method of making the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a high-K dielectric material and a dielectric precursor material to form a composite layer having at least two sub-layers of at least one of the high-K dielectric material and the dielectric precursor material. The semiconductor device may be subjected to annealing at an elevated temperature to form a composite dielectric layer from the composite layer.
摘要翻译：一种半导体器件和制造具有复合介电层的半导体器件的方法，包括提供半导体衬底的步骤; 在半导体衬底上沉积高K电介质材料和电介质前体材料的交替子层，以形成具有至少两个高K电介质材料和电介质前体材料之一的子层的复合层。可以在升高的温度下对半导体器件进行退火以从复合层形成复合介电层。

26. 发明授权

US06376323B1 Fabrication of gate of P-channel field effect transistor with added implantation before patterning of the gate 有权
标题翻译：在栅极图案化之前加入P沟道场效应晶体管的栅极的制造
公开(公告)号：US06376323B1
公开(公告)日：2002-04-23
申请号：US09825819
申请日：2001-04-04
申请人： Hyeon-Seag Kim , Joong Jeon
发明人： Hyeon-Seag Kim , Joong Jeon
IPC分类号： H01L21331
CPC分类号： H01L21/28035 , H01L21/823842 , H01L21/823857
摘要： For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material containing nitrogen is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A first P-type dopant, such as boron for example, is implanted into a first region of the layer of gate electrode material disposed over a first active device area of the semiconductor substrate. The first region of the layer of gate electrode material is patterned to form a PMOS gate electrode. The layer of gate dielectric material is patterned to form a PMOS gate dielectric disposed under the PMOS gate electrode. A second P-type dopant, such as boron fluoride (BF2) for example, is implanted into the PMOS gate electrode and into the exposed regions of the first active device area of the semiconductor substrate to form a drain extension junction and a source extension junction of the PMOS field effect transistor. The boron as the first P-type dopant is a lighter dopant than boron fluoride (BF2) and thus distributes more evenly throughout the layer of gate electrode material. The nitrogen within the gate dielectric material below the layer of gate electrode material prevents diffusion of the boron out of the gate electrode material and into the gate dielectric. Thus, a depletion region is less likely to form toward the bottom of the gate electrode near the gate dielectric. The boron fluoride (BF2) as the second P-type dopant that is relatively heavier is used to form shallow drain and source extensions to minimize short channel effects of the PMOS field effect transistor.
摘要翻译：为了在半导体衬底上制造PMOS（P沟道金属氧化物半导体）场效应晶体管，在半导体衬底上沉积含有氮的栅极介电材料层，并且在栅极电介质层上沉积一层栅电极材料材料。诸如硼的第一P型掺杂剂例如注入设置在半导体衬底的第一有源器件区域上的栅电极层的第一区域中。图案化栅极材料层的第一区域以形成PMOS栅电极。栅极介电材料层被图案化以形成设置在PMOS栅电极下方的PMOS栅极电介质。例如，诸如氟化硼（BF 2）的第二P型掺杂剂注入PMOS栅电极并注入到半导体衬底的第一有源器件区域的暴露区域中，以形成漏极延伸结和源极延伸结的PMOS场效应晶体管。作为第一P型掺杂剂的硼是比氟化硼（BF 2）更轻的掺杂剂，因此更均匀地分配在整个栅极电极材料层上。位于栅电极材料层下方的栅极电介质材料内的氮阻止硼从栅电极材料中扩散并进入栅极电介质。因此，耗尽区域不太可能在栅极电介质附近的栅极电极的底部形成。用作相对较重的第二P型掺杂剂的氟化硼（BF 2）用于形成浅的漏极和源极延伸，以最小化PMOS场效应晶体管的短沟道效应。

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