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21. 发明授权

US06504764B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US06504764B2
公开(公告)日：2003-01-07
申请号：US09985116
申请日：2001-11-01
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In a read command, the control circuit reads data in the memory cells and outputs it. In a write command, the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.
摘要翻译：具有多个存储单元和控制电路的非易失性存储器件。控制电路从设备外部接收操作命令，并根据命令控制设备的操作。命令包括读命令和写命令。在读命令中，控制电路读取存储单元中的数据并将其输出。在写入命令中，控制电路控制数据到数据锁存电路的输入，然后控制到存储单元。控制电路提供指示数据写入是成功还是失败的状态信息。

22. 发明授权

US06490195B2 Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell 失效
标题翻译：半导体器件，数据处理系统和用于改变非易失性存储单元的阈值的方法
公开(公告)号：US06490195B2
公开(公告)日：2002-12-03
申请号：US09965800
申请日：2001-10-01
申请人： Michitaro Kanamitsu , Tetsuya Tsujikawa , Toshinori Harada , Hiroaki Kotani , Shoji Kubono , Atsushi Nozoe , Takayuki Yoshitake
发明人： Michitaro Kanamitsu , Tetsuya Tsujikawa , Toshinori Harada , Hiroaki Kotani , Shoji Kubono , Atsushi Nozoe , Takayuki Yoshitake
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C2211/5621 , G11C2211/5642
摘要： Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.
摘要翻译：基于输入到数据锁存电路（DLR和DLL）的附加写入数据和从存储器单元（MC）读取的数据，将写入状态的非易失性存储器单元编程为相同写入状态并编程非易失性存储器处于擦除状态的单元变成由附加写入数据指示的写入状态。所生成的数据被锁存在数据锁存电路中以执行用于附加写入的逻辑合成处理。即使在附加写入操作之后，逻辑合成的数据保留在数据锁存电路中，并且锁存的数据可以被反复用于写入异常。这样就不需要再次从外部再次接收写入数据。

23. 发明授权

US06320793B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US06320793B2
公开(公告)日：2001-11-20
申请号：US09820906
申请日：2001-03-30
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.
摘要翻译：具有多个存储单元和控制电路的非易失性存储器件。控制电路从设备外部接收操作命令，并根据命令控制设备的操作。命令包括读命令和写命令。在读命令中，控制电路读取存储单元中的数据并将其输出。在写命令中，控制电路控制数据到数据锁存电路的输入，然后控制到存储单元。控制电路提供指示数据写入是成功还是失败的状态信息。

24. 发明授权

US6046936A Semiconductor, memory card, and data processing system 有权
公开(公告)号：US6046936A
公开(公告)日：2000-04-04
申请号：US250157
申请日：1999-02-16
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

25. 发明授权

US06721207B2 Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches 有权
标题翻译：非易失性存储器系统，包括用于控制包括存储器单元和数据锁存器的非易失性器件的写入，读取和存储和输出操作的控制装置
公开(公告)号：US06721207B2
公开(公告)日：2004-04-13
申请号：US10211342
申请日：2002-08-05
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G51C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.
摘要翻译：非易失性存储器系统设置有控制设备和非易失性存储器设备，每个包括存储器单元和数据锁存器。控制装置向非易失性存储装置提供包括写入命令以及第一和第二读取命令的命令。当控制装置向写入命令提供写入地址信息和用于存储在非易失性存储器件中的数据时，它将数据存储到数据锁存器，然后存储到存储器单元，然后验证存储器。当控制装置向读取地址信息提供第一读取命令时，非易失性存储器件将存储在存储器单元中的数据读取到数据锁存器，然后将数据锁存器中的数据输出到控制装置。当控制装置提供第二读取命令时，非易失性存储装置将数据锁存器中的数据输出到控制装置。

26. 发明授权

US06507520B2 Nonvolatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US06507520B2
公开(公告)日：2003-01-14
申请号：US10011723
申请日：2001-12-11
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.
摘要翻译：外部提供的程序数据被锁存在数据锁存电路DLL和DLR中。在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。

27. 发明授权

US06456526B2 Non-volatile memory device operation in response to two different types of read commands and a write command which includes write verification 有权
标题翻译：响应于两种不同类型的读取命令的非易失性存储器件操作和包括写入验证的写入命令
公开(公告)号：US06456526B2
公开(公告)日：2002-09-24
申请号：US09820894
申请日：2001-03-30
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.
摘要翻译：具有多个存储单元和控制电路的非易失性存储器件。控制电路从设备外部接收操作命令，并根据命令控制设备的操作。命令包括读命令和写命令。在读命令中，控制电路读取存储单元中的数据并将其输出。在写命令中，控制电路控制数据到数据锁存电路的输入，然后控制到存储单元。控制电路提供指示数据写入是成功还是失败的状态信息。

28. 发明授权

US6078519A Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell 有权
公开(公告)号：US6078519A
公开(公告)日：2000-06-20
申请号：US317976
申请日：1999-05-25
申请人： Michitaro Kanamitsu , Tetsuya Tsujikawa , Toshinori Harada , Hiroaki Kotani , Shoji Kubono , Atsushi Nozoe , Takayuki Yoshitake
发明人： Michitaro Kanamitsu , Tetsuya Tsujikawa , Toshinori Harada , Hiroaki Kotani , Shoji Kubono , Atsushi Nozoe , Takayuki Yoshitake
IPC分类号： G11C16/02 , G11C11/34 , G11C16/00 , G11C16/04 , G11C29/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C2211/5621 , G11C2211/5642
摘要： Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.

29. 发明授权

US06999348B2 Nonvolatile semiconductor storage unit 有权
标题翻译：非易失性半导体存储单元
公开(公告)号：US06999348B2
公开(公告)日：2006-02-14
申请号：US10501391
申请日：2002-02-28
申请人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
发明人： Michitaro Kanamitsu , Yoshinori Takase , Shoji Kubono
IPC分类号： G11C11/34
CPC分类号： G11C16/26
摘要： A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.
摘要翻译：非易失性半导体存储单元可以通过采用能够减小面积（减少元件数量）的单端感测系统来防止感测锁存电路中的错误检测操作。提供了使用单端感测系统和NMOS栅极感测系统的闪存芯片。在单端感测系统中，感测锁存电路连接到全局位线的一端以检测对应于存储器单元的阈值电压的全局位线上的数据。 NMOS栅极感测系统使用NMOSFET在栅极处的全局位线上接收数据，并驱动用于感测锁存电路的节点。 NMOSFET感测感测电压。感测锁存电路在确保足够的信号量的情况下被激活。来自施加电源的阈值电压的输出电压预充电全局位线。以这种方式，可以始终保持NMOSFET的预充电电压和阈值电压之间的恒定差。

30. 发明授权

US06765840B2 Nonvolatile semiconductor memory and read method 失效
标题翻译：非易失性半导体存储器和读取方法
公开(公告)号：US06765840B2
公开(公告)日：2004-07-20
申请号：US10357477
申请日：2003-02-04
申请人： Hiroshi Sato , Shoji Kubono , Toshinori Harada , Takayuki Kawahara , Naoki Miyamoto
发明人： Hiroshi Sato , Shoji Kubono , Toshinori Harada , Takayuki Kawahara , Naoki Miyamoto
IPC分类号： G11C700
CPC分类号： G11C11/5621 , G11C7/1048 , G11C11/5642 , G11C2211/5642
摘要： In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
摘要翻译：在通过设定多个阈值将多值信息存储在一个存储单元中的非易失性半导体存储器中，从字线连续读取数据，同时连续地将字线读取电平从最低级别改变到最高级，并且根据存储在用于存储读取数据的锁存装置中的数据来选择性地预充电下一位线。

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