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21. 发明授权

US07609792B2 Multiple-input multiple-output multichip transceiver with correlated clock signals 失效
标题翻译：具有相关时钟信号的多输入多输出多芯片收发器
公开(公告)号：US07609792B2
公开(公告)日：2009-10-27
申请号：US11069172
申请日：2005-03-01
申请人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard B. Nicholls , Keith A. Holt , Stanley K. Ling
发明人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard B. Nicholls , Keith A. Holt , Stanley K. Ling
IPC分类号： H04B7/10
CPC分类号： H04L1/06
摘要： A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.
摘要翻译：多芯片收发器作为多输入多输出通信系统的一部分而工作。第一集成电路上的第一接收器电路处理从第一信号源接收的射频（RF）信号，第二集成电路上的第二接收器电路处理从第二信号源接收的RF信号。时钟信号产生电路通过相位匹配的路径提供时钟信号到第一和第二接收器电路。

22. 发明授权

US08941520B2 Resistor-based Σ-ΔDAC 有权
标题翻译：基于电阻和电阻的DAC
公开(公告)号：US08941520B2
公开(公告)日：2015-01-27
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/08 , H03M1/80 , H03M1/78 , H03M1/74 , H03M1/00 , H03M1/12 , G09G3/36
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

23. 发明授权

US08736384B2 Delay line calibration 有权
标题翻译：延迟线校准
公开(公告)号：US08736384B2
公开(公告)日：2014-05-27
申请号：US12769806
申请日：2010-04-29
申请人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala , Masoud Sajadieh
发明人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala , Masoud Sajadieh
IPC分类号： H03L7/095
CPC分类号： H03L7/1978
摘要： In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.
摘要翻译：在一些实施例中，提供了用于测量TDL延迟级元件之间的不匹配的校准技术，并且在一些情况下，然后补偿不匹配以最小化性能下降。

24. 发明授权

US08098726B2 Subranging for a pulse position and pulse width modulation based transmitter 有权
标题翻译：基于脉冲位置和基于脉宽调制的发射机的分组
公开(公告)号：US08098726B2
公开(公告)日：2012-01-17
申请号：US12176646
申请日：2008-07-21
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Itshak Hod , Yorgos Palaskas , Masoud Sajadieh
IPC分类号： H03K7/08
CPC分类号： H03K7/10 , H03F3/2178 , H04B1/0483 , H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, in a pulse position and pulse position modulation out-phasing transmitter, the range of the phase angle, theta, may be divided into more than one range to drive a first power amplifier with a first range of theta, and to drive a second power amplifier with a second range of theta. In one or more embodiments, a main power amplifier is driven with a first phase range having a higher probability density function, and an overload power amplifier is driven with a first phase range having a lower probability density function. In one or more embodiments, a full adder may be used to combine the two phases wherein the sum signal is used to drive the main power amplifier, and the carry signal is used to drive the overload power amplifier.
摘要翻译：简而言之，根据一个或多个实施例，在脉冲位置和脉冲位置调制输出相位变送器中，相位角θ的范围可被划分成多于一个范围以驱动具有第一范围的第一功率放大器的θ，并驱动具有θ的第二范围的第二功率放大器。在一个或多个实施例中，主功率放大器由具有较高概率密度函数的第一相位范围驱动，而过载功率放大器由具有较低概率密度函数的第一相位范围驱动。在一个或多个实施例中，全加器可以用于组合两相，其中求和信号用于驱动主功率放大器，并且进位信号用于驱动过载功率放大器。

25. 发明申请

US20150074156A1 METHODS AND SYSTEMS TO COMPENSATE FOR NON-LINEARITY OF A STOCHASTIC SYSTEM 有权
标题翻译：补偿系统非线性的方法和系统
公开(公告)号：US20150074156A1
公开(公告)日：2015-03-12
申请号：US14022683
申请日：2013-09-10
申请人： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
发明人： Ofir Degani , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： G06F5/00 , G06F17/18
CPC分类号： G06F5/00 , G04F10/005 , H03L7/085 , H03L2207/50 , H03M1/1014 , H03M1/1033
摘要： Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop.
摘要翻译：基于随机系统响应于线性相位斜坡生成的校准数据的统计分析，确定数字补偿以补偿配置为采样相位差的随机系统的非线性。随机系统可以包括一组随机采样器电路，以在周期性事件中采样相位差，并且校准数据可以包括多个事件中的每一个的随机样本集合的数字值。校准数据可以包括数字值的序列，其中数字值在随机系统的范围（即，随机系统的饱和状态之间）增加。统计分析可以包括直方图分析来估计校准数据的概率分布。随机系统可以被配置为时间 - 数字转换器的一部分，其可以配置在数字可控锁相环的反馈回路内。

26. 发明授权

US08390349B1 Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter 有权
标题翻译：次皮秒分辨率分段重新循环随机时间 - 数字转换器
公开(公告)号：US08390349B1
公开(公告)日：2013-03-05
申请号：US13533341
申请日：2012-06-26
申请人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
发明人： Ashoke Ravi , Ofir Degani , Hyung Seok Kim , Hasnain Lakdawala , Yee W. Li , Paolo Madoglio
IPC分类号： H03L7/06
CPC分类号： G04F10/005 , H03L2207/50
摘要： Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.
摘要翻译：公开了一种将TDC分辨率提高到1ps而不引起匹配和功率损失的方法和装置。可以通过在不匹配的循环时间数字转换器（RTDC）和随机时间 - 数字转换器（STDC）之间分辨分辨率来实现更高的分辨率。所公开的RTDC复制相同的延迟元件以消除与所需动态范围（对于5GHz示例为200ps）和中等分辨率（3-5ps典型对应于5GHz情况下的6-7位）的失配。虽然STDC可以实现50 fs的分辨率，但只有3-5 ps的范围，这也通过利用过程变化和失配来对应于大约6-7个附加位，以获得有限动态范围的非常精细的分辨率。

27. 发明授权

US07773669B2 Cascaded phase pulse position and pulse width modulation based digital transmitter 有权
标题翻译：级联相位脉冲位置和基于脉宽调制的数字发射器
公开(公告)号：US07773669B2
公开(公告)日：2010-08-10
申请号：US11837043
申请日：2007-08-10
申请人： Ofir Degani , Hasnain Lakdawala , Ashoke Ravi
发明人： Ofir Degani , Hasnain Lakdawala , Ashoke Ravi
IPC分类号： H03K7/04
CPC分类号： H04L25/4902
摘要： Briefly, in accordance with one or more embodiments, a digital transmitter may comprise two or more phase modulators in a cascaded arrangement. The phase modulators may modulate a local oscillator signal using control signals derived from the quadrature baseband data to be transmitted. A closed loop power control feedback arrangement may be used to compare the output power of the transmitter with a desired output signal, and make corrections to the output signal by modifying at least one of the control signals provided to the cascaded phase modulators.
摘要翻译：简而言之，根据一个或多个实施例，数字发射机可以包括两个或更多个级联布置的相位调制器。相位调制器可以使用从要发送的正交基带数据导出的控制信号来调制本地振荡器信号。可以使用闭环功率控制反馈装置来将发射机的输出功率与期望的输出信号进行比较，并且通过修改提供给级联相位调制器的控制信号中的至少一个来对输出信号进行校正。

28. 发明申请

US20090036064A1 DIGITAL INTEGRATED TRANSMITTER BASED ON FOUR-PATH PHASE MODULATION 审中-公开
标题翻译：基于四路相位调制的数字集成发射机
公开(公告)号：US20090036064A1
公开(公告)日：2009-02-05
申请号：US11831017
申请日：2007-07-31
申请人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
发明人： Ashoke Ravi , Ofir Degani , Hasnain Lakdawala
IPC分类号： H04B1/40 , H04L27/20
CPC分类号： H03C3/40
摘要： Briefly, in accordance with one or more embodiments, a transmitter comprises four phase modulators to provide four path phase modulation. The phase modulators modulate local oscillator signals with control signals derived from quadrature baseband data to be transmitted to result in four phase modulated signals. The four phase modulated signals may be combined to provide a pulse position and pulse width modulated signal that may have a constant, or nearly constant, amplitude. The frequency spectrum of the control signals have narrower bandwidths and greater out of band attenuation resulting in higher suppression of out of channel and out of band noise.
摘要翻译：简而言之，根据一个或多个实施例，发射机包括四个相位调制器以提供四路径相位调制。相位调制器用来自正交基带数据的控制信号调制本地振荡器信号，以传输四个相位调制信号。可以组合四个相位调制信号以提供可以具有恒定或接近恒定幅度的脉冲位置和脉宽调制信号。控制信号的频谱具有较窄的带宽和较大的带外衰减，从而导致通道和带外噪声的更高的抑制。

29. 发明授权

US08222966B2 System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband RF outphasing/polar transmitters 有权
标题翻译：用于宽带RF外相/极性发射机的开环校准相位缠绕相位调制器的系统，方法和装置
公开(公告)号：US08222966B2
公开(公告)日：2012-07-17
申请号：US12879152
申请日：2010-09-10
申请人： Ashoke Ravi , Paolo Madoglio , Marian Verhelst , Georgios Palaskas
发明人： Ashoke Ravi , Paolo Madoglio , Marian Verhelst , Georgios Palaskas
IPC分类号： H03C3/02 , H03K7/06 , H04B1/02
CPC分类号： H03C3/20 , H03C3/10 , H03K5/133
摘要： A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.
摘要翻译：用于开环校准相位缠绕相位调制器的器件制品和方法。抽头延迟线可以为信号的一个或多个相位提供粗分辨率。相位多路复用器可以从抽头延迟线接收一个或多个粗略相位，并选择粗略相位以发送到数字控制的延迟线。数字控制的延迟线可以从相位多路复用器提供到粗略相位的精细分辨率。

30. 发明申请

US20060198476A1 Multiple-input multiple-output multichip transceiver with correlated clokc signals 失效
标题翻译：具有相关clokc信号的多输入多输出多芯片收发器
公开(公告)号：US20060198476A1
公开(公告)日：2006-09-07
申请号：US11069172
申请日：2005-03-01
申请人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard Nicholls , Keith Holt , Stanley Ling
发明人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard Nicholls , Keith Holt , Stanley Ling
IPC分类号： H04L1/02
CPC分类号： H04L1/06
摘要： A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.
摘要翻译：多芯片收发器作为多输入多输出通信系统的一部分而工作。第一集成电路上的第一接收器电路处理从第一信号源接收的射频（RF）信号，第二集成电路上的第二接收器电路处理从第二信号源接收的RF信号。时钟信号产生电路通过相位匹配的路径提供时钟信号到第一和第二接收器电路。

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