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21. 发明专利

JPS62274765A PROTECTIVE CIRCUIT AGAINST STATIC ELECTRICITY 失效
公开(公告)号：JPS62274765A
公开(公告)日：1987-11-28
申请号：JP11734086
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ETO JUN , MIYAZAWA KAZUYUKI , KIMURA KATSUTAKA , WATANABE YASUSHI , SHIMOHIGASHI KATSUHIRO
IPC分类号： H01L29/78 , H01L21/822 , H01L27/02 , H01L27/04
摘要： PURPOSE:To raise the static breakdown strength without increasing the chip area as well as the delay time of input signals by a method wherein a layer of the same conductivity type as that of a substrate while in higher concentration than that of the substrate is provided coming into contact with and below a resistance diffused layer with a conductivity type opposite to that of the semiconductor substrate. CONSTITUTION:When a node N1 is supplied with a surge voltage in the negative direction, a current i3 flows from generating terminal N4 through resistors Rsub, R; another current i4 flows through resistors RS, R; and an input terminal N2 of inner circuit is supplied with a voltage of Rs/(R+Rs).i4. A P type layer is provided below an N layer so that the breakdown voltage VD of diode may be lowered while reducing Rsub to increase i3. Resultantly, i4 can be decreased to supply a node N2 with low surge voltage. Through these procedures, the surge voltage can be lowered without increasing the value of resistor R as well as gm of MOSFET, T to raise the static breakdown strength.

22. 发明专利

JPH02224267A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02224267A
公开(公告)日：1990-09-06
申请号：JP4301489
申请日：1989-02-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MUSHA TATSUNORI , HORIGUCHI SHINJI , TANAKA HITOSHI , ETO JUN , AOKI MASAKAZU , ITO KIYOO
IPC分类号： H01L27/04 , G11C11/401 , G11C11/407 , H01L21/822
摘要： PURPOSE:To reduce parasitic impedance between a bonding pad and an internal reference voltage generator circuit by disposing said internal reference voltage generator circuit in the vicinity of the ground input bonding pad. CONSTITUTION:A voltage limiter circuit is divided into an internal reference voltage generator circuit 6 and a drive circuit 7, and the internal reference voltage generator circuit 6 is disposed in the vicinity of a ground input bonding pad 4. Hereby, parasitic impedance of a ground wiring 9 can be reduced and highly accurate internal reference voltage stable against ground noise can be yielded. Further, an internal reference voltage wiring 10 can reduce any noise from the adjacent wiring layer using a shielding line, and is made stable against power supply noise because of parasitic capacity possessed by the shielding line.

23. 发明专利

JP2000331490A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000331490A
公开(公告)日：2000-11-30
申请号：JP13763099
申请日：1999-05-18
申请人： HITACHI LTD , MITSUBISHI ELECTRIC CORP , HITACHI ULSI SYS CO LTD
发明人： SONOYAMA HIROSHI , KAWAJIRI YOSHIKI , WADA MASASHI , ETO JUN , KAWAI SHINJI
IPC分类号： G11C16/06 , G01R19/165 , G05F1/56 , G05F3/24 , G11C5/14 , G11C16/30 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To greatly improve the reliability of a semiconductor integrated circuit device by reducing the dispersion of detection levels in power source voltage caused by temperature, a manufacturing process and the like. SOLUTION: The voltage difference between reference voltage VREF generated by a reference voltage generating section 16 and detection voltage to which power source voltage VCC is voltage-divided by resistors 27, 28 is amplified differentially by a differential amplifying circuit SA and outputted as a detection signal K. Since the reference voltage generating section 16 generates reference voltage VREF from the voltage between a base and an emitter in a bipolar type transistor in which dispersion caused by temperature and a manufacturing process is small, dispersion of a detection level in power source voltage VCC can be made small.

24. 发明专利

JP2000076887A Semiconductor apparatus 有权
标题翻译： SEMICONDUCTOR APPARATUS
公开(公告)号：JP2000076887A
公开(公告)日：2000-03-14
申请号：JP20421899
申请日：1999-07-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , ETO JUN , AOKI MASAKAZU , ITO KIYOO
IPC分类号： G11C29/04 , G11C11/401 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To save defects with a small area and a large improvement effect in yield by setting the number (m) of word lines or bit lines to be replaced simultaneously by the defect relief to be an M's divisor smaller than M when a memory area is divided to M memory mats.
SOLUTION: Memory mats 100-103 comprise areas 110-113 wherein normal memory cells are arranged and areas 120-123 where backup memory cells are arranged. NW×NB'/4 memory cells are arranged at intersections of NW/2 word lines W and NB/2 bit lines of the areas 110-113. L×NB/2 backup memory cells are arranged at intersections of L (L=2 in this case) spare word lines SW and NB/2 bit lines of the areas 120-123. Since the number of memory cells to be replaced simultaneously is reduced, a probability that backup memory cells replacing the normal memory cells are defective is smaller and a yield is improved.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了通过将缺陷缓解的同时被替换的字线数或位线的数量（m）设定为小于M的M的除数，则通过将小的面积的缺陷和良好的改善效果保存为小于M的M 存储区分为M个内存垫。解决方案：存储器垫100-103包括其中布置有正常存储器单元的区域110-113，并且布置备份存储器单元的区域120-123。 NW×NB'/ 4个存储单元被布置在区域110-113的NW / 2字线W和NB / 2位线的交点处。 L×NB / 2备用存储单元被布置在区域120-123的L（L = 2）的备用字线SW和NB / 2位线的交点处。由于同时更换的存储器单元的数量减少，所以替换正常存储器单元的备用存储器单元的可能性较小，并且提高了产量。

25. 发明专利

JPH11265986A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH11265986A
公开(公告)日：1999-09-28
申请号：JP8804098
申请日：1998-03-17
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： MURAKAMI HITOSHI , KASAI HIDEO , CHICHII MIKIO , KOSAKAI KENJI , KAWAJIRI YOSHIKI , ETO JUN
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To achieve the low cost of flash memories and the like by enhancing the arranging efficiency of logic cells and wiring in logic circuit parts such as the flash memories, reducing the size of the chip, increasing the lines of the cells provided in the logic circuit parts at the same time and increasing the number of the logic cells that can be provided at the respective cell lines. SOLUTION: In the flash memory and the like having a memory array MARY and a logic circuit part LOGC and having gate layers SG and metal wiring layers M1 and M2 of the first layer and the second layer as the wiring layers, cell lines CL1-CL8 of the logic circuit part LOGC are arranged at the perpendicular direction for the rectangular close side in the arranging pattern of the memory array MARY, that is, the lower short side. At the same time, gate layers SG and first-layer metal wiring layers M1 are arranged as the wirings in the cell. As the power-supply wiring for each logic cell 1 and the wiring channel for the wiring between the cells, the first-layer metal wiring layer M1 is used. As the outgoing wiring between the logic cell and the wiring channel, the gate layer SG is used. Thus, the second metal wiring layer M2 can be arranged in the arbitral direction on the upper layer of the logic cell as the wiring between the cells.

26. 发明专利

JPH0927199A NON-VOLATILE STORAGE DEVICE AND ITS REFRESHING METHOD 失效
公开(公告)号：JPH0927199A
公开(公告)日：1997-01-28
申请号：JP17257495
申请日：1995-07-07
申请人： HITACHI LTD
发明人： KOSAKAI KENJI , FURUSAWA KAZUNORI , ETO JUN , NAKAMURA YASUHIRO , YUGAWA YOSUKE , IZAWA KAZUTO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C29/00 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To obtain a non-volatile storage device which can stably operate by making a dispersion distribution state of threshold voltage steep by performing rewriting for a memory cell which is discriminated as a defective cell for writing. SOLUTION: When an erasing/rewriting processing program is performed by a MPU 20, an address generating section 90 generates the first X address, and outputs it to an address bus 115. Also, a verifying potential from a verifying power source 70, for example, 5V is applied to a word line of the address through a X decoder 105, data is read out. Read out data is transferred to an evacuation register 40. Successively, an erasing verifying potential set to, for example, 3V is sent to a verified word line, read out data is transferred to a data discriminating section 50. Next, both data read out by 3V and 5V are compared by the discriminating section 50, a bit in which both data does not coincide is detected, and self restoration of a defective cell is performed.

27. 发明专利

JPH07245558A INPUT CIRCUIT FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07245558A
公开(公告)日：1995-09-19
申请号：JP3330594
申请日：1994-03-03
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , ETO JUN , SAKATA TAKESHI , TAKEUCHI MIKI , MATSUNO KATSUMI , AOKI MASAKAZU
IPC分类号： H03K19/0175 , G11C11/407 , G11C11/408 , H03K5/24
摘要： PURPOSE:To attain high speed operation by eliminating the need for a timing margin from fetch of an input signal till a latch output in the input circuit of the semiconductor device such as an address buffer. CONSTITUTION:An address buffer 100 is made up of a differential amplifier 10 receiving an input signal Ai and providing an output of a couple of differential signals AiT, AiB and a survival latch circuit 20 detecting a signal changed earlier in the differential signals and latching and outputting the detected signal. Furthermore, activation/inactivation of the differential amplifier 10 is made depending on ON/OFF of an N channel MOS transistor(TR) M9 based on a Set signal. A voltage is produced between the differential signals when the differential amplifier 10 is activated and both the differential signals go to a low level when the differential amplifier 10 is inactivated.

28. 发明专利

JPH06162798A DYNAMIC RAM 失效
公开(公告)号：JPH06162798A
公开(公告)日：1994-06-10
申请号：JP8969493
申请日：1993-04-16
申请人： HITACHI LTD
发明人： MIYAZAWA KAZUYUKI , SHIMOHIGASHI KATSUHIRO , ETO JUN , KIMURA KATSUTAKA
IPC分类号： G11C29/00 , G11C11/401 , G11C29/14
摘要： PURPOSE:To quickly perform the test without increasing the external terminals by discriminating a required combination of external control signals to set the test mode and detecting coincidence/discordance of a read signal consisting of plural bits. CONSTITUTION:An FF is set by a timing generating circuit TG, which lets a column address strobe signal CAS and a write enable signal WE be at a low level at the falling timing of a row address strobe signal RAS, to let a test mode signal TE be H. Test circuits included in a data input circuit DIB and a data output circuit DOB respectively are made to be in the operating state, and coincidence/discordance at each bit for 4-bit data read out from a memory cell array (x4) M-ARY is detected by the test circuit of the circuit DOB; and if discordance of even one bit is detected, the corresponding output signal is sent to an external terminal DOUT. By this constitution, it is unnecessary to increase the external terminals, and the test speed is improved in the unit of plural bits.

29. 发明专利

JPH0576720B2 失效
公开(公告)号：JPH0576720B2
公开(公告)日：1993-10-25
申请号：JP13712784
申请日：1984-07-04
申请人： HITACHI LTD
发明人： ETO JUN , HORI RYOICHI , ITO KYOO
IPC分类号： G11C11/407 , G11C11/34 , G11C11/401 , G11C11/408

30. 发明专利

JPH02192100A SEMICONDUCTOR MEMORY DEVICE WITH DEFECT RELIEVE CIRCUIT 失效
公开(公告)号：JPH02192100A
公开(公告)日：1990-07-27
申请号：JP26002189
申请日：1989-10-06
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , ETO JUN , AOKI MASAKAZU , ITO KIYOO
IPC分类号： G11C29/00 , G11C11/34 , G11C11/401 , G11C11/413 , G11C29/04
摘要： PURPOSE:To enlarge the improving effect of yield in a small area by setting the number (m) of word lines or bit lines, which are simultaneously replaced by defect relief, to the divisor of M smaller than the M when a memory array is divided into the M (M>=2) number of memory mats. CONSTITUTION:For example, when a word line W[i, 0] of a memory mat 110 is selected, a word line W[i, 2] corresponding to a memory mat 112 is simultaneously selected. When the word lines of memory mats 111 and 113 are selected, the word lines of the memory mats 110 and 112 are not selected. For example, when a word line W[0, 0] of the memory part 110 is defective, W[0, 0] and W[0, 2] are simultaneously replaced with an auxiliary word line. However, the word lines of the memory mats 111 and 113 are not replaced. Thus, the number of the memory cells to be simultaneously replaced by the defect relief is reduced. Then, the probability of the defect in the auxiliary line itself is reduced, the improving effect of the yield is made large even in a highly integrated memory.

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