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21. 发明申请

WO1998036419A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO1998036419A1
公开(公告)日：1998-08-20
申请号：PCT/JP1997000410
申请日：1997-02-17
申请人： HITACHI, LTD. , AYUKAWA, Kazushige , WATANABE, Takao , NARITA, Susumu
发明人： HITACHI, LTD.
IPC分类号： G11C11/407
CPC分类号： G06F12/0215 , G06F13/1631 , G11C7/1072 , G11C8/12 , G11C11/005
摘要： A memory macro (MM) is a combination of functional modules such as a main amplifier module (13), memory bank modules (11) of which each memory bank operates independently, a power source circuit (14), etc. The storage capacity of the memory macro (MM) can be easily changed from a large capacity to a small one by changing the number of the memory bank modules (11). A control circuit (BKCONTH) in the memory bank modules (11) of the memory macro (MM) has an additional address comparing function (COMP). Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro (MM). In addition, a module (17) having a function such as a memory access sequence control is provided and, when memory access is made, identification information (ID) is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.
摘要翻译：存储器宏（MM）是功能模块的组合，诸如主放大器模块（13），每个存储器组独立地存储的存储体模块（11），电源电路（14）等。存储容量通过改变存储体模块（11）的数量，可以容易地将存储器宏（MM）从大容量改变为小容量。存储器宏（MM）的存储器组模块（11）中的控制电路（BKCONTH）具有附加地址比较功能（COMP）。因此，可以高速访问同一页面，而不需要在存储器宏（MM）之外提供任何控制电路。此外，提供具有诸如存储器访问顺序控制的功能的模块（17），并且当进行存储器访问时，在输入/输出地址或数据时发出识别信息（ID）。因此，可以通过使用ID检查数据和地址之间的一致性并控制存储器访问顺序来实现高速存储器访问，从而可以改变地址输入顺序和数据输出顺序。

22. 发明申请

WO1998033275A1 INPUT BUFFER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND BOARD SYSTEM 审中-公开
标题翻译：输入缓存电路，半导体集成电路和板系统
公开(公告)号：WO1998033275A1
公开(公告)日：1998-07-30
申请号：PCT/JP1997000123
申请日：1997-01-22
申请人： HITACHI, LTD. , SHIOZAWA, Kenji , KUDOU, Ikuo , ISHIBASHI, Koichiro , IZAWA, Ryuichi
发明人： HITACHI, LTD.
IPC分类号： H03K19/0185
CPC分类号： H01L27/0251 , H01L27/092 , H03K19/018528
摘要： A differential stage includes a reference input p-MOSFET and a signal input p-MOSFET that is connected at its drain to a voltage-controlled variable level shifting circuit. The drain of the reference input MOSFET and the level shifting circuit are connected to a current mirror circuit that is grounded on the other end. The current mirror circuit applies a reference potential to the level shifting circuit as well as serving as a load on the reference input MOSFET. In this configuration, the gate-drain voltage and the gate-substrate voltage of the signal input MOSFET, whose substrate is maintained at the drain voltage, will not exceed an allowable level if an input signal is higher in level than the supply voltage. As a result, device reliability is improved.
摘要翻译：差分级包括参考输入p-MOSFET和在其漏极连接到电压可变电平移位电路的信号输入p-MOSFET。参考输入MOSFET和电平移位电路的漏极连接到另一端接地的电流镜电路。电流镜电路将参考电位施加到电平移位电路以及用作参考输入MOSFET上的负载。在这种配置中，如果输入信号的电平高于电源电压，则其基板保持在漏极电压的信号输入MOSFET的栅极 - 漏极电压和栅极 - 基板电压将不会超过允许电平。结果，提高了设备的可靠性。

23. 发明申请

WO1998032186A1 SODIUM-SULFUR BATTERY MODULE 审中-公开
标题翻译： SODIUM-SULFUR电池模块
公开(公告)号：WO1998032186A1
公开(公告)日：1998-07-23
申请号：PCT/JP1997000061
申请日：1997-01-16
申请人： HITACHI, LTD. , HIRANUMA, Takeshi , TOKOI, Hiromi , WATAHIKI, Naohisa
发明人： HITACHI, LTD.
IPC分类号： H01M10/39
CPC分类号： H01M10/3909
摘要： A sodium-sulfur battery module comprising batteries (1) separated by spaces filled up with an insulating liquid (3) which does not react with sodium and sulfur, wherein a recovering device (5) prevents the short circuit between adjacent batteries by removing an active material, such as the sodium or sulfur leaking into the liquid or sodium polysulfide, etc., and removes heat from the batteries or equalizes the temperatures of adjacent batteries by circulating the liquid. Therefore, the module can be continuously operated even when some of the batteries are out of order and, at the same time, the batteries are protected from damage by stabilizing their characteristics and temperature.
摘要翻译：一种钠硫电池模块，包括由填充有不与钠和硫反应的绝缘液体（3）的间隔分开的电池（1），其中回收装置（5）通过去除活性物质来防止相邻电池之间的短路材料，例如泄漏到液体中的钠或硫或多硫化钠等，并且从电池中除去热量或通过循环液体来均衡相邻电池的温度。因此，即使一些电池故障，也可以连续运行模块，同时通过稳定其特性和温度来保护电池免受损坏。

24. 发明申请

WO1998029908A1 FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：电磁存储器件及其制造方法
公开(公告)号：WO1998029908A1
公开(公告)日：1998-07-09
申请号：PCT/JP1997004778
申请日：1997-12-24
申请人： HITACHI, LTD. , OGATA, Kiyoshi , HORIKOSHI, Kazuhiko , SUENAGA, Kazufumi , KATO, Hisayuki , YOSHIZUMI, Keiichi , YAMAZAKI, Masahito
发明人： HITACHI, LTD.
IPC分类号： H01L27/10
CPC分类号： H01L28/57 , H01L27/1203
摘要： A ferroelectric memory device in which a ferroelectric thin film capacitor is used as a memory capacitor includes one or more of an upper protective electrode, a deterioration preventing layer on an upper electrode (8), and interface deterioration preventive layers between a ferroelectric layer (7) and an electrode (6) and between the ferroelectric layer (7) and the upper electrode (8). A modified layer at the interface between the ferroelectric layer (7) and the upper electrode (8) is reduced instead. The ferroelectric thin film is hardly fatigued and imprinted, the characteristics of the ferroelectric body deteriorate little, and the life of the ferroelectric memory device is long.
摘要翻译：其中使用铁电薄膜电容器作为存储电容器的铁电存储器件包括上电极（8）中的上保护电极，劣化防止层中的一个或多个，以及强电介质层（7）之间的界面劣化防止层）和电极（6）之间并且在铁电层（7）和上电极（8）之间。在铁电层（7）和上电极（8）之间的界面处的改性层被减小。铁电薄膜几乎不疲劳和压印，铁电体的特性变差，铁电存储器件的寿命长。

25. 发明申请

WO1998029833A1 PATTERN RECOGNITION APPARATUS AND PATTERN RECOGNITION METHOD 审中-公开
标题翻译：模式识别装置和模式识别方法
公开(公告)号：WO1998029833A1
公开(公告)日：1998-07-09
申请号：PCT/JP1996003789
申请日：1996-12-25
申请人： HITACHI, LTD. , MITSUYAMA, Satoshi , MOTOIKE, Jun , MATSUO, Hitoshi , KOJIMA, Yasuaki
发明人： HITACHI, LTD.
IPC分类号： G06T07/00
CPC分类号： G06K9/00127 , G06K9/6217 , G06K9/6263
摘要： The image characteristic values and classification results of an object of which the classification results are outputted by first pattern recognition means (110) in accordance with the judgment that the reliability of the recognition results is high and the object is recognizable are stored in recognizable data storage means (130). The image characteristic values of an object of which the reliability of the recognition results is judged to be low and the recognition is suspended are stored in recognition suspension data storage means (120). Pattern recognition method constitution means (140) constitutes second pattern recognition means (150) on the basis of the classification results stored in the recognizable data storage means (130), and reclassification is carried out on the object whose recognition is judged to be suspended. A neural network is used as the second pattern recognition means (150), for example. Wrong classification of the object due to the individual difference hardly occurs and pattern recognition is conducted with high accuracy independent of the individual difference, automatically.
摘要翻译：根据识别结果的可靠性高且对象可识别的判断，由第一模式识别装置（110）输出分类结果的对象的图像特征值和分类结果被存储在可识别的数据存储器手段（130）。将识别结果的可靠性判断为低并且识别被暂停的对象的图像特征值存储在识别暂停数据存储装置（120）中。模式识别方法构成装置（140）基于存储在可识别数据存储装置（130）中的分类结果构成第二模式识别装置（150），并且对被识别被判断为暂停的对象进行重新分类。例如，使用神经网络作为第二模式识别装置（150）。由于个体差异，对象的错误分类几乎不发生，并且自动执行独立于个体差异的高精度的模式识别。

26. 发明申请

WO1998027454A1 TRANSVERSE ELECTRIC FIELD SYSTEM LIQUID CRYSTAL DISPLAY DEVICE SUITABLE FOR IMPROVING APERTURE RATIO 审中-公开
标题翻译：横向电场系统液晶显示装置适用于改善孔径比
公开(公告)号：WO1998027454A1
公开(公告)日：1998-06-25
申请号：PCT/JP1996003691
申请日：1996-12-18
申请人： HITACHI, LTD. , OHTA, Masuyuki , OGAWA, Kazuhiro , ASHIZAWA, Keiichiro , YANAGAWA, Kazuhiko , YANAI, Masahiro , KONISHI, Nobutake , SUZUKI, Nobuyuki , ISHII, Masahiro , YONEYA, Makoto , ARATANI, Sukekazu
发明人： HITACHI, LTD.
IPC分类号： G02F01/1343
CPC分类号： G02F1/134363
摘要： An active matrix type liquid crystal display device capable of accomplishing an angle of visual field equal to that of a CRT and controlling the display by an electric field substantially parallel to a substrate surface provides bright display and requires lower power consumption. Pixel electrodes and opposed electrode capable of applying an electric field substantially parallel to a substrate surface is constituted, the pixel electrodes or the opposed electrodes are constituted by transparent electrodes, and the orientation state of a liquid crystal and the axis of polarization of a polarizer are constituted so that dark display is effected at the time when no field is applied. In this way, there can be provided a transverse field system active matrix type liquid crystal display device having a wide visual field angle characteristics, excellent contrast ratio and aperture ratio and capable of improving maximum transmissivity.
摘要翻译：能够实现与CRT相同的视野角的有源矩阵型液晶显示装置，并且通过与基板表面大致平行的电场来控制显示，能够提供明亮的显示，并且需要更低的功耗。像素电极和能够施加大致平行于基板表面的电场的相对电极构成，像素电极或相对电极由透明电极构成，液晶的取向状态和偏振片的偏振轴为构成为使得在不施加场的时候进行暗显示。以这种方式，可以提供具有宽的视场角特性，优异的对比度和孔径比的横向场系统有源矩阵型液晶显示装置，并能够提高最大透射率。

27. 发明申请

WO1998026458A1 INSULATED GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：绝缘栅半导体器件
公开(公告)号：WO1998026458A1
公开(公告)日：1998-06-18
申请号：PCT/JP1997004538
申请日：1997-12-10
申请人： THE KANSAI ELECTRIC POWER CO., INC. , HITACHI, LTD. , SUGAWARA, Yoshitaka , ASANO, Katsunori
发明人： THE KANSAI ELECTRIC POWER CO., INC. , HITACHI, LTD.
IPC分类号： H01L29/78
CPC分类号： H01L29/1095 , H01L29/0623 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7397 , H01L29/7398 , H01L29/7809 , H01L29/7811 , H01L29/7813
摘要： In a semiconductor device having a trench type insulated gate structure, in the case where a drift layer (2) of an n conduction type has a high carrier concentration, when a high voltage is applied between a drain and a source in such a manner that a channel is not formed, the electric field strength of an insulator layer (9) below the trench type insulated gate is increased, thus causing breakdown. The withstand voltage of the semiconductor device is limited by the breakdown of the insulator layer (9), and it is difficult to realize high withstand voltage. Thus, a field relaxation semiconductor region (1) of a conduction type opposite to the conduction type of the drift layer (2) is formed within the drift layer (2) below the insulator layer (9) in the trench of the trench type insulated gate semiconductor device. Also, the thickness of a bottom portion of the insulator layer (9) provided in the trench of the trench type insulated gate semiconductor device is made significantly greater than the thickness of a lateral portion thereof.
摘要翻译：在具有沟槽型绝缘栅极结构的半导体器件中，在n导电类型的漂移层（2）具有高载流子浓度的情况下，当在这样的漏极和源极之间施加高电压时不形成沟道的方式，沟槽型绝缘栅下方的绝缘体层（9）的电场强度增加，从而导致击穿。半导体器件的耐压受到绝缘体层（9）的击穿的限制，难以实现高耐压。因此，在沟槽型绝缘的沟槽中的绝缘体层（9）下方的漂移层（2）内形成与漂移层（2）的导电类型相反的导电类型的场弛豫半导体区域（1）门半导体器件。此外，设置在沟槽型绝缘栅极半导体器件的沟槽中的绝缘体层（9）的底部的厚度被制成明显大于其侧面部分的厚度。

28. 发明申请

WO1998025849A1 ELEVATOR CONTROL DEVICE AND CONTROL DEVICE FOR POWER CONVERTER 审中-公开
标题翻译：电梯转换器的电梯控制装置和控制装置
公开(公告)号：WO1998025849A1
公开(公告)日：1998-06-18
申请号：PCT/JP1996003613
申请日：1996-12-11
申请人： HITACHI, LTD. , MUTOH, Nobuyoshi , HOKARI, Sadao
发明人： HITACHI, LTD.
IPC分类号： B66B01/30
CPC分类号： B66B1/30
摘要： In an elevator adapted to be driven by a converter connected to a system power source, a smoothing capacitor for smoothing an output of the converter, a PWN inverter for converting voltage of the smoothing capacitor into an alternating current of variable frequency and variable voltage, and a motor supplied by the inverter with power, an elevator control device comprises a solar battery, a capacitor of large capacity power of at least several Farads capable of accumulating an instantaneous output power generated by the solar battery, and output voltage regulating means for regulating an output voltage of the capacitor, and the elevator control device acts to feed generated power of the solar battery into the smoothing capacitor and enables a voltage control system of the converter to use energy generated by the solar battery as energy for operation of the elevator and automatically return surplus energy to a commercial power source.
摘要翻译：在适于由连接到系统电源的转换器驱动的电梯中，用于平滑转换器的输出的平滑电容器，用于将平滑电容器的电压转换为可变频率和可变电压的交流电的PWN反相器，以及由逆变器供电的电动机，电梯控制装置包括太阳能电池，能够积聚太阳能电池产生的瞬时输出功率的至少几个法拉的大容量电力的电容器，以及用于调节太阳能电池的输出电压调节装置电容器的输出电压，并且电梯控制装置用于将太阳能电池的发电功率馈送到平滑电容器中，并且使得转换器的电压控制系统能够使用由太阳能电池产生的能量作为电梯的操作的能量并且自动地将剩余能量返还给商业电源。

29. 发明申请

WO1998025304A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO1998025304A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003549
申请日：1996-12-04
申请人： HITACHI, LTD. , MIYAMOTO, Toshio , NISHIMURA, Asao , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu , SHIBA, Kazuyoshi
发明人： HITACHI, LTD.
IPC分类号： H01L25/065
CPC分类号： H01L23/49816 , H01L23/49572 , H01L25/0657 , H01L25/105 , H01L27/10814 , H01L27/10894 , H01L27/118 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/13091 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H01L2924/3511 , H01L2224/0401
摘要： A multilayered package in which a plurality of tape carriers where semiconductor chips are mounted are stacked. One end of each of leads formed on one side of each tape carrier is electrically connected to one of the connecting terminals of the semiconductor chips, and the other end of each of the leads are electrically connected to one of the through holes made in the carriers. The connecting terminals which are common to the semiconductor chips are formed at an area of the carriers and led to the external connecting terminals through the through holes.
摘要翻译：堆叠安装半导体芯片的多个带载体的多层封装。形成在每个带载体的一侧上的每个引线的一端电连接到半导体芯片的一个连接端子，并且每个引线的另一端电连接到在载体中形成的通孔之一。半导体芯片共用的连接端子形成在载体的区域并通过通孔导向外部连接端子。

30. 发明申请

WO1998025271A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO1998025271A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003548
申请日：1996-12-04
申请人： HITACHI, LTD. , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu , MIYAMOTO, Toshio , NISHIMURA, Asao
发明人： HITACHI, LTD.
IPC分类号： G11C11/407
CPC分类号： G11C11/409 , G11C11/406
摘要： A semiconductor integrated circuit device for high-speed data transfer, wherein wait control is eliminated to allow a logic circuit to access a DRAM during the self-refreshing period of the DRAM. The integrated circuit comprises a chip that includes a microcomputer incorporated with a CPU, memories and peripheral circuits, and a flash memory; and another chip that includes DRAMs and a logic circuit, such as an ASIC. The control of the DRAM depends on whether the DRAM is in the normal access period or in the self-refreshing period. In the DRAM self-refreshing period, the refreshing operations are canceled so that the logic circuit can access the DRAM when the logic circuit requests the access to the DRAM by using readout/write signals R/W.
摘要翻译：一种用于高速数据传输的半导体集成电路装置，其中消除了等待控制，以允许逻辑电路在DRAM的自刷新周期期间存取DRAM。集成电路包括芯片，其包括与CPU结合的微计算机，存储器和外围电路以及闪速存储器; 以及包括DRAM和诸如ASIC的逻辑电路的另一芯片。 DRAM的控制取决于DRAM是处于正常访问周期还是在自刷新期间。在DRAM自刷新周期中，刷新操作被取消，使得当逻辑电路通过使用读出/写入信号R / W请求访问DRAM时逻辑电路可以访问DRAM。

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