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21. 发明授权

US5500810A Filter device with memory test circuit 失效
标题翻译：带内存测试电路的滤波器
公开(公告)号：US5500810A
公开(公告)日：1996-03-19
申请号：US231766
申请日：1994-04-25
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： H03H15/00 , H03H17/02 , G06F15/31
CPC分类号： H03H17/0291 , H03H15/00
摘要： A filter device with memory test circuit easily executes a memory test inspite of single-bit data processing to 1 bit data. The filter device with a memory test circuit includes a memory test circuit between a memory means and a shift register, sequentially reads digital data and tests digital data at the external Central Processing Unit (CPU) after converting the data from parallel to serial at the shift register.
摘要翻译：具有存储器测试电路的滤波器器件容易地执行单位数据处理到1位数据的存储器测试。具有存储器测试电路的滤波器装置包括存储器装置和移位寄存器之间的存储器测试电路，在将数据从并行转换为串行数据之后顺序读取数字数据并在外部中央处理器（CPU）测试数字数据寄存器。

22. 发明授权

US5452336A Memory device for recording a time factor 失效
标题翻译：用于记录时间因素的记忆装置
公开(公告)号：US5452336A
公开(公告)日：1995-09-19
申请号：US151030
申请日：1993-11-12
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G04G99/00 , G11C27/00 , H03M1/56 , H03M1/58 , H03K21/02 , H03K17/30
CPC分类号： H03M1/58 , H03M1/56
摘要： A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.
摘要翻译：用于记录数据的时间因子的存储器件包括阈值元件，耦合电容，RC电路和数字计数器。参考电压被输入到RC电路。 RC电路的输出和输入电压各自输入到耦合电容。耦合电容的输出被输入到阈值元件。当由阈值元件接收的电压达到阈值电压电平时，阈值元件产生输出电压。数字计数器接收阈值元件输出电压和参考电压。数字计数器由参考电压触发，开始计数由参考时钟产生的时钟脉冲。数字计数器然后由阈值元件输出电压触发，以停止对时钟脉冲的计数。

23. 发明授权

US5424965A Multiplication circuit for multiplying analog values 失效
标题翻译：用于乘法运算的乘法电路
公开(公告)号：US5424965A
公开(公告)日：1995-06-13
申请号：US172393
申请日：1993-12-23
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/16 , G06J1/00
CPC分类号： G06J1/00
摘要： A multiplication circuit for multiplying analog values. The multiplication circuit receives a plurality of input voltages and selects one of the input voltages. The multiplication circuit also includes at least one resistor/capacitor (RC) circuit. The RC circuits includes a resistor for receiving a stepwise start signal and a capacitor, which is connected between a ground potential and the resistor. An output terminal is connected between the resistor and the capacitor. The output terminal outputs an output voltage. The multiplication circuit produces a stop signal when a difference between the selected one of the input voltages and the output voltage is greater than a predetermined value. The multiplication circuit selectively increases or decreases a count value by a number of clock pulses that occur between the stepwise start signal and the stop signal, The multiplication circuit produces a count signal, which is indicative of the count value. The multiplication circuit includes a switch for electrically disconnecting, in accordance with the count signal, the resistor and the capacitor of the RC circuit.
摘要翻译：用于乘以模拟值的乘法电路。乘法电路接收多个输入电压并选择输入电压之一。乘法电路还包括至少一个电阻器/电容器（RC）电路。 RC电路包括用于接收逐步启动信号的电阻器和连接在接地电位和电阻器之间的电容器。输出端连接在电阻和电容之间。输出端输出输出电压。当选择的输入电压和输出电压之间的差异大于预定值时，乘法电路产生停止信号。乘法电路选择性地将计数值增加或减少在逐步启动信号和停止信号之间发生的时钟脉冲数。乘法电路产生计数信号，其表示计数值。乘法电路包括根据计数信号电路断开RC电路的电阻器和电容器的开关。

24. 发明授权

US5396446A Digital filter circuit that minimizes holding errors transmitted between holding circuits 失效
标题翻译：数字滤波电路使保持电路之间传输的保持误差最小化
公开(公告)号：US5396446A
公开(公告)日：1995-03-07
申请号：US155809
申请日：1993-11-23
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06J1/00 , H03H17/02 , G06G7/02
CPC分类号： H03H17/0294 , G06J1/00 , H03H17/0225
摘要： A filter circuit that controls holding errors so that such errors are held to a minimum. In the filter circuit, multipliers of multiplication circuits are stored in a shift register and multiplication is successively executed with various multipliers in a multiplication circuit by circulating multipliers in the shift register.
摘要翻译：控制保持误差使得将这些误差保持在最小的滤波器电路。在滤波器电路中，乘法电路的乘法器存储在移位寄存器中，并且通过在移位寄存器中循环乘法器，在乘法电路中通过各种乘法器连续执行乘法运算。

25. 发明授权

US5381352A Circuit for multiplying an analog value by a digital value 失效
标题翻译：将模拟值乘以数字值的电路
公开(公告)号：US5381352A
公开(公告)日：1995-01-10
申请号：US170731
申请日：1993-12-21
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/16 , G06J1/00 , H03M1/80
CPC分类号： G06J1/00 , H03M1/804
摘要： A multiplication circuit directly multiplying an analog and a digital data without converting analog/digital or digital/analog converting. An analog input voltage is controlled by a switching signal of a digital voltage so as to generate an analog output or cut-off the outputs. Digital input signals b.sub.0 to b.sub.7 of a plural number of bits is integrated giving weights by means of a capacitive coupling, and a sign bit is added by a capacitive coupling CP with a double weight of the most significant bit ("MSB") of the digital input.
摘要翻译：乘法电路将模拟和数字数据直接相乘，而无需转换模拟/数字或数字/模拟转换。模拟输入电压由数字电压的开关信号控制，以产生模拟输出或截止输出。多个位的数字输入信号b0至b7被积分，通过电容耦合给出加权，并且通过电容耦合CP加上符号位，该电容耦合CP具有最高有效位（“MSB”）的双重权重数字输入

26. 发明授权

US5974038A Receiver for code division multiple access communication system 失效
标题翻译：接收机用于码分多址通信系统
公开(公告)号：US5974038A
公开(公告)日：1999-10-26
申请号：US864784
申请日：1997-05-29
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04B1/707 , H04B1/7075 , H04B1/7093 , H04B1/7115 , H04L7/00 , H04B7/216
CPC分类号： H04B1/708 , H04B1/7093 , H04B1/7115 , H04B2201/70709
摘要： This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.
摘要翻译：本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号。此外，进行解扩。来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

27. 发明授权

US5930290A Spread spectrum communications system for high-speed communications 失效
标题翻译：扩频通信系统，用于高速通信
公开(公告)号：US5930290A
公开(公告)日：1999-07-27
申请号：US841217
申请日：1997-04-30
申请人： Changming Zhou , Guoliang Shou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori , Kenzo Urabe
发明人： Changming Zhou , Guoliang Shou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori , Kenzo Urabe
IPC分类号： H04B1/707 , H04B1/7093 , H04J13/10 , H04B15/00 , H04B7/216
CPC分类号： H04J13/0077 , H04B1/7093
摘要： A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.
摘要翻译：提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。要发送的一系列数字数据被分为4位帧。每帧的4位数据按预定顺序分成第一至第四元素。第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。要传输的数据的频谱通过乘以这些复数来传播。四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。根据匹配滤波器的输出，恢复第一至第四元件。

28. 发明授权

US5872466A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5872466A
公开(公告)日：1999-02-16
申请号：US686950
申请日：1996-07-26
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03H11/04 , H03H17/02 , H04B1/707 , H04B1/7093 , H04L7/00 , H04L7/10 , H03K5/00
CPC分类号： H03H11/04 , H03H17/0254
摘要： A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.
摘要翻译：公开了具有降低的电力消耗的匹配滤波器。由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。各组中的信号通过电容耦合并联并且在电路中间歇地供电。

29. 发明授权

US5783961A Inverted amplifying circuit 失效
标题翻译：反相放大电路
公开(公告)号：US5783961A
公开(公告)日：1998-07-21
申请号：US764637
申请日：1996-12-11
申请人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03K19/0948 , H03F1/02 , H03F1/34 , H03F3/46 , H03F3/72 , H03K5/153 , H03H11/26
CPC分类号： H03F3/72
摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.
摘要翻译：本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。当反相放大电路不工作时，MOS开关打开。

30. 发明授权

US5734583A Capacitance forming method 失效
标题翻译：电容成型法
公开(公告)号：US5734583A
公开(公告)日：1998-03-31
申请号：US536326
申请日：1995-09-29
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H01L27/08 , H01L27/10 , G06F17/50
CPC分类号： H01L27/0805 , H01L27/101
摘要： A capacitance forming method for forming capacitances corresponding to a plurality of constant numbers within a large scale integrated circuit (LSI) comprises steps of defining a unit capacitance with a predetermined shape, defining an arrangement of a plurality of the unit capacitances of a number necessary for total capacity of capacitances to be formed in two dimension in an area of the LSI, selecting the unit capacitances of a number corresponding to the maximal capacity among capacities of the capacitances to be formed so that the selected unit capacitances are equivalently dispersed over the area, and successively selecting other of the capacitances than the capacitance of the maximal capacity in the order of capacities, and selecting the unit capacitances of a number corresponding to a capacity of each the capacitance selected so that the selected unit capacitances are equivalently dispersed over an area of the rest of the unit capacitances which have not selected yet.
摘要翻译：用于在大规模集成电路（LSI）内形成对应于多个常数的电容的电容形成方法包括以预定形状定义单位电容的步骤，限定多个单位电容的排列，在LSI的区域中形成二维电容的总容量，选择与要形成的电容的容量之间的最大容量相对应的数字的单位电容，使得所选择的单位电容等效地分散在该区域上，并且依次选择电容量以及容量顺序的最大容量的电容量，并且选择与所选择的每个电容的容量对应的数量的单位电容，使得所选择的单位电容等价地分散在其余单位电容尚未选择。

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