专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5892980A System for dynamically changing the length of transmit and receive sample buffers utilizing previous responding to an interrupt in a communications system 失效
标题翻译：用于使用先前响应通信系统中的中断来动态地改变发送和接收采样缓冲器的长度的系统
公开(公告)号：US5892980A
公开(公告)日：1999-04-06
申请号：US808071
申请日：1997-02-28
申请人： Nir Tal , Ron Cohen , Zeev Collin
发明人： Nir Tal , Ron Cohen , Zeev Collin
IPC分类号： G06F13/00 , H04L5/14 , H04L13/08 , G06F13/14 , G06F13/20
CPC分类号： H04L5/14
摘要： An apparatus for and method of implementing a novel buffer based fall duplex communication system is disclosed. The disclosed invention is particularly useful in native signal processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel dynamic buffer size mechanism to optimize the tradeoff between buffer delay and processing time period, on one hand, and robustness to interrupt latency and processor availability on the other hand. Small buffers provide the communication system with short, accurate response times in addition to short processing times. Using a large buffer of spare or dummy samples to be transmitted while the CPU is unavailable reduces the probability of a buffer underrun, thus giving the operating system greater leeway in deciding the exact time the signal processing functions in the modem routine are run. In this manner latency time is held to a minimum and data is not lost or corrupted. The concept of using dummy bits or silence for the generation of spare samples enables the elimination of additional latency caused by the spare samples by overriding them if they are not transmitted. This is achieved without a loss of signal coherency.
摘要翻译：公开了一种实现基于新型缓冲器的秋季双工通信系统的方法和方法。所公开的发明特别适用于其中通常存在大量竞争的处理器资源的本机信号处理系统，例如在运行多任务操作系统的系统中。本发明的通信系统包括接收机，发射机，CODEC和电话混合。系统的主要组件在由一组输入位组成的输入采样的缓冲器上操作。通信系统用于产生由一组输出位组成的输出采样的缓冲器。本发明一方面利用了一种新颖的动态缓冲大小机制来优化缓冲延迟与处理时间之间的权衡，另一方面优化了中断延迟和处理器可用性的鲁棒性。小型缓冲器为通信系统提供了短时间，准确的响应时间以及短的处理时间。在CPU不可用的情况下使用大量的备用或虚拟样本缓冲区可以减少缓冲区欠载的可能性，从而使操作系统在决定调制解调器例程中的信号处理功能运行的确切时间方面有更大的余地。以这种方式将延迟时间保持在最低限度，数据不会丢失或损坏。使用虚拟位或静音来生成备用样本的概念使得能够通过在备用样本未被传输时重写备用样本来消除额外的等待时间。这是在不损失信号一致性的情况下实现的。

22. 发明授权

US08121558B2 Local oscillator generator architecture using a wide tuning range oscillator 有权
标题翻译：使用宽调谐范围振荡器的本地振荡器发生器架构
公开(公告)号：US08121558B2
公开(公告)日：2012-02-21
申请号：US12118769
申请日：2008-05-12
申请人： Gireesh Rajendran , Nir Tal , Ashish Lachhwani
发明人： Gireesh Rajendran , Nir Tal , Ashish Lachhwani
IPC分类号： H04B1/40 , H04B1/26 , H03L7/00
CPC分类号： H03B21/01
摘要： A local oscillator (LO) generator architecture using a wide tuning range oscillator is disclosed. In one embodiment, a wide tuning oscillator based LO generator system includes a wide tuning range oscillator for generating a signal with a first initial frequency or a second initial frequency in response to a control voltage, a first frequency controlling circuit for converting the first initial frequency of the signal into a final frequency, and a second frequency controlling circuit for converting the second initial frequency of the signal into the final frequency.
摘要翻译：公开了使用宽调谐范围振荡器的本地振荡器（LO）发生器架构。在一个实施例中，基于宽调谐振荡器的LO发生器系统包括宽调谐范围振荡器，用于响应于控制电压产生具有第一初始频率或第二初始频率的信号;第一频率控制电路，用于将第一初始频率的信号转换成最终频率;以及第二频率控制电路，用于将信号的第二初始频率转换成最终频率。

23. 再颁专利

USRE40497E1 Communication system which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency 有权
标题翻译：通信系统，动态切换采样缓冲区的大小，用于快速响应时间和第二大小，以提高中断延迟
公开(公告)号：USRE40497E1
公开(公告)日：2008-09-09
申请号：US09771010
申请日：2001-01-26
申请人： Nir Tal , Ron Cohen , Zeev Collin
发明人： Nir Tal , Ron Cohen , Zeev Collin
IPC分类号： G06F13/14
CPC分类号： H04M11/06 , H04L7/005
摘要： An apparatus for and method of implementing a novel buffer ba full duplex communication system is disclosed. The disclosed invention is particularly useful in native sign processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, echo canceler. CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communications system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel buffer switching mechanism to optimize the tradeoff between processing response time, on one hand, and robustness to interrupt latency and processor implementation on the other hand. The internal processing of the modem works on a buffer full of samples once every time slice thus reducing the probability of a buffer underrun/overrun error occurring. The reduction in probability of data underrun/overrun is achieved by increasing the buffer size, thus giving the operating system greater leeway in choosing the exact time the signal processing functions are run. Small buffers, however, provide the communication system with short and accurate response time. These contradicting motives lead to the novel switchable size buffer scheme of the present invention. This is achieved without a loss of signal coherency.
摘要翻译：公开了一种实现新型缓冲器全双工通信系统的方法和方法。所公开的发明在诸如在运行多任务操作系统的系统中通常存在大量竞争的处理器资源的本征符号处理系统中特别有用。本发明的通信系统包括接收机，发射机，回波消除器。 CODEC和电话混合。系统的主要组件在由一组输入位组成的输入采样的缓冲器上操作。通信系统用于产生由一组输出位组成的输出采样的缓冲器。本发明利用新颖的缓冲器切换机制来优化处理响应时间，另一方面优化中断延迟和处理器实现的鲁棒性之间的权衡。调制解调器的内部处理工作在每次采样一次的样本缓冲区中，从而降低缓冲区欠载/超限错误发生的可能性。通过增加缓冲区大小来实现数据欠载/超载的概率的降低，从而使操作系统在选择信号处理功能的精确时间方面具有更大的余地。然而，小缓冲器为通信系统提供了短且准确的响应时间。这些矛盾的动机导致本发明的新颖的可切换尺寸的缓冲方案。这是在不损失信号一致性的情况下实现的。

24. 发明申请

US20080043818A1 Fast Hopping Frequency Synthesizer Using an All Digital Phased Locked Loop (ADPLL) 有权
标题翻译：使用全数字相位锁定环（ADPLL）的快速跳频合成器
公开(公告)号：US20080043818A1
公开(公告)日：2008-02-21
申请号：US11856829
申请日：2007-09-18
申请人： Nir Tal , Robert Staszewski , Ofer Friedman
发明人： Nir Tal , Robert Staszewski , Ofer Friedman
IPC分类号： H04B1/00 , H04B1/40
CPC分类号： H04B1/7136 , H03C3/40 , H03D3/007 , H03L7/08 , H03L7/0991 , H04B1/71635 , H04B1/71637 , H04B2001/71365
摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.
摘要翻译：一种新颖有用的快速频率合成器和发射机。频率合成器和发射器包含适用于操作开环的数字控制振荡器（DCO）。通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。在一个实施例中，DCO可以在用于构造DCO的变容二极管装置的1 / f T T中瞬时改变频率。在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。开关期间的任何相移都由发射机中的数字电路跟踪。在第二实施例中，通过使用有效地产生有效地移动合成频率的精细分辨率复指数波形的数控振荡器（NCO）来提供额外的频率精度。混频器在转换为数字域之前将波形应用于I和Q数据采样。

25. 发明授权

US5909384A System for dynamically adapting the length of a filter 失效
标题翻译：用于动态调整过滤器长度的系统
公开(公告)号：US5909384A
公开(公告)日：1999-06-01
申请号：US726187
申请日：1996-10-04
申请人： Nir Tal , Nir Shapira , Ron Cohen
发明人： Nir Tal , Nir Shapira , Ron Cohen
IPC分类号： H03H21/00 , G06F17/10 , H04B3/23 , H04L25/03 , H04M9/08
CPC分类号： G06F17/10 , H04B3/23 , H04M9/082 , H04L2025/03585
摘要： A novel system by which the utilization of a central processing unit (CPU) in performing filtering operations can be reduced by shortening the filter's length thus degrading the performance of the system down to a predetermined level or threshold. The present invention is applicable to such systems that incorporate filters whereby shortening their length decreases the performance of the system and to such systems where a reliable quality criteria exists that can be measured during run time. A method iteratively minimizes the filter's length so that the quality criteria does not fall below a predetemined threshold level. In addition, a signal to noise ratio (SN) criteria is suggested for estimating the quality of the reception of communication signals. An implementation is suggested for the method in the particular case of an echo cancellation adaptive filter. In addition, a method for determining an immediate approximation of the echo canceler filter's length as opposed to finding it iteratively.
摘要翻译：可以通过缩短过滤器的长度，从而降低系统的性能降到预定的水平或阈值，从而可以减少利用中央处理单元（CPU）进行滤波操作的新型系统。本发明可应用于包括过滤器的这种系统，由此缩短其长度降低了系统的性能以及存在可在运行时间期间测量的可靠质量标准的系统。一种方法迭代地最小化过滤器的长度，使得质量标准不会低于预定阈值水平。另外，建议信噪比（SN）准则用于估计通信信号的接收质量。在回波消除自适应滤波器的特定情况下，建议用于该方法的实现。另外，用于确定回波消除器滤波器的长度的立即近似的方法，而不是迭代地发现它。

26. 发明申请

US20080144707A1 TRANSMITTER BUILT-IN PRODUCTION LINE TESTING UTILIZING DIGITAL GAIN CALIBRATION 有权
标题翻译：发射机内置生产线测试利用数字增益校准
公开(公告)号：US20080144707A1
公开(公告)日：2008-06-19
申请号：US11949611
申请日：2007-12-03
申请人： Yossi Tsfati , Nir Tal , Avi Baum , Itay Sherman
发明人： Yossi Tsfati , Nir Tal , Avi Baum , Itay Sherman
IPC分类号： H04B17/00 , H04B1/40
CPC分类号： H04B17/13
摘要： A novel and useful self-calibration based production line testing mechanism utilizing built-in closed loop measurements in the radio to calibrate the output power of an external power amplifier coupled to a SoC radio. The mechanism is applicable during production line testing and calibration which is performed on each SoC and associated external power amplifier after assembly at the target PCB of the final product. The mechanism calibrates the TX output power in three phases based on loopback EVM measurements. In a first phase, the PPA in the radio (SoC) is calibrated and gain versus output power is stored in a gain table in on-chip NVS. In a second phase, the maximum PPA TX power is determined using closed loop EVM measurements. The external PA is calibrated in a third phase and the maximum PA power is determined. During this third phase, the maximum power of the device is calculated, compared to the requirements of the particular standard and a pass/fail determination is thereby made.
摘要翻译：一种基于自适应校准的基于自校准的生产线测试机制，在无线电中利用内置闭环测量来校准耦合到SoC无线电的外部功率放大器的输出功率。该机制适用于在最终产品的目标PCB上组装之后在每个SoC和相关外部功率放大器上执行的生产线测试和校准。该机制基于环回EVM测量三相校准TX输出功率。在第一阶段，无线电（SoC）中的PPA被校准，并且增益对输出功率被存储在片上NVS的增益表中。在第二阶段，使用闭环EVM测量确定最大PPA TX功率。外部PA在第三阶段进行校准，并确定最大PA功率。在第三阶段期间，与特定标准的要求相比，计算出装置的最大功率，从而进行通过/不合格确定。

27. 发明授权

US6108720A Echo canceling modem which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency 有权
标题翻译：回波消除调制解调器，动态切换样本缓冲区的大小，用于快速响应时间和第二大小，以提高中断延迟
公开(公告)号：US6108720A
公开(公告)日：2000-08-22
申请号：US163054
申请日：1998-09-29
申请人： Nir Tal , Ron Cohen , Zeev Collin
发明人： Nir Tal , Ron Cohen , Zeev Collin
IPC分类号： G06F13/00 , H04L13/08 , H04L29/10 , H04M11/00 , H04M11/06 , H04B1/38 , H04B1/44 , H04L5/16 , H04M1/00
CPC分类号： H04M11/06 , H04L7/005
摘要： An apparatus for and method of implementing a novel buffer based full duplex communication system is disclosed. The disclosed invention is particularly useful in native signal processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, echo canceler, CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel buffer switching mechanism to optimize the tradeoff between processing response time, on one hand, and robustness to interrupt latency and processor implementation on the other hand. The internal processing of the modem works on a buffer full of samples once every time slice thus reducing the probability of a buffer underrun/overrun error occurring. The reduction in probability of data underrun/overrun is achieved by increasing the buffer size, thus giving the operating system greater leeway in choosing the exact time the signal processing functions are run. Small buffers, however, provide the communication system with short and accurate response time. These contradicting motives lead to the novel switchable size buffer scheme of the present invention. This is achieved without a loss of signal coherency.
摘要翻译：公开了一种实现基于新型缓冲器的全双工通信系统的装置和方法。所公开的发明特别适用于其中通常存在大量竞争的处理器资源的本机信号处理系统，例如在运行多任务操作系统的系统中。本发明的通信系统包括接收机，发射机，回波消除器，CODEC和电话混合。系统的主要组件在由一组输入位组成的输入采样的缓冲器上操作。通信系统用于产生由一组输出位组成的输出采样的缓冲器。本发明利用新颖的缓冲器切换机制来优化处理响应时间，另一方面优化中断延迟和处理器实现的鲁棒性之间的权衡。调制解调器的内部处理工作在每次采样一次的样本缓冲区中，从而降低缓冲区欠载/超限错误发生的可能性。通过增加缓冲区大小来实现数据欠载/超载的概率的降低，从而使操作系统在选择信号处理功能的精确时间方面具有更大的余地。然而，小缓冲器为通信系统提供了短且准确的响应时间。这些矛盾的动机导致本发明的新颖的可切换尺寸的缓冲方案。这是在不损失信号一致性的情况下实现的。

28. 发明授权

US07701997B2 Fast hopping frequency synthesizer using an all digital phased locked loop (ADPLL) 有权
标题翻译：使用全数字锁相环（ADPLL）的快速跳频合成器
公开(公告)号：US07701997B2
公开(公告)日：2010-04-20
申请号：US11856829
申请日：2007-09-18
申请人： Nir Tal , Robert B. Staszewski , Ofer Friedman
发明人： Nir Tal , Robert B. Staszewski , Ofer Friedman
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713
CPC分类号： H04B1/7136 , H03C3/40 , H03D3/007 , H03L7/08 , H03L7/0991 , H04B1/71635 , H04B1/71637 , H04B2001/71365
摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.
摘要翻译：一种新颖有用的快速频率合成器和发射机。频率合成器和发射器包含适用于操作开环的数字控制振荡器（DCO）。通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。在一个实施例中，DCO可以在用于构造DCO的变容二极管装置的1 / fT内瞬间改变频率。在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。开关期间的任何相移都由发射机中的数字电路跟踪。在第二实施例中，通过使用有效地产生有效地移动合成频率的精细分辨率复指数波形的数控振荡器（NCO）来提供额外的频率精度。混频器在转换为数字域之前将波形应用于I和Q数据采样。

29. 发明申请

US20090280752A1 LOCAL OSCILLATOR GENERATOR ARCHITECTURE USING A WIDE TUNING RANGE OSCILLATOR 有权
标题翻译：本地振荡器发电机结构使用宽调谐范围振荡器
公开(公告)号：US20090280752A1
公开(公告)日：2009-11-12
申请号：US12118769
申请日：2008-05-12
申请人： Gireesh Rajendran , Nir Tal , Ashish Lachhwani
发明人： Gireesh Rajendran , Nir Tal , Ashish Lachhwani
IPC分类号： H04B1/40 , H03B21/01
CPC分类号： H03B21/01
摘要： A local oscillator (LO) generator architecture using a wide tuning range oscillator is disclosed. In one embodiment, a wide tuning oscillator based LO generator system includes a wide tuning range oscillator for generating a signal with a first initial frequency or a second initial frequency in response to a control voltage, a first frequency controlling circuit for converting the first initial frequency of the signal into a final frequency, and a second frequency controlling circuit for converting the second initial frequency of the signal into the final frequency.
摘要翻译：公开了使用宽调谐范围振荡器的本地振荡器（LO）发生器架构。在一个实施例中，基于宽调谐振荡器的LO发生器系统包括宽调谐范围振荡器，用于响应于控制电压产生具有第一初始频率或第二初始频率的信号;第一频率控制电路，用于将第一初始频率的信号转换成最终频率;以及第二频率控制电路，用于将信号的第二初始频率转换成最终频率。

30. 发明申请

US20080055008A1 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation with jitter estimation and correction 有权
标题翻译：振荡器和RF频率之间具有非谐波比的本地振荡器，使用具有抖动估计和校正的异或运算
公开(公告)号：US20080055008A1
公开(公告)日：2008-03-06
申请号：US11844425
申请日：2007-08-24
申请人： Robert B. Staszewski , Nir Tal
发明人： Robert B. Staszewski , Nir Tal
IPC分类号： H03B21/01 , H03B21/00
CPC分类号： H03B21/00
摘要： A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.
摘要翻译：本地振荡器（LO）生成的新颖有用的装置和方法，其本地振荡器和RF频率之间具有非整数倍乘比。所呈现的LO产生方案可用于以指定频率产生I和Q方波，同时避免众所周知的谐波拉动问题。避免使用现有技术的模拟混频器，并用配置成产生正确的平均频率的XOR门代替。根据受控振荡器的分频时钟的状态，边沿被动态调整±T / 12或零。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式