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21. 发明授权

US06845033B2 Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology 失效
标题翻译：用于沟槽技术的双晶体管和双电容器存储单元的结构和片上系统集成
公开(公告)号：US06845033B2
公开(公告)日：2005-01-18
申请号：US10248954
申请日：2003-03-05
申请人： Toshiaki Kirihata , John W. Golz
发明人： Toshiaki Kirihata , John W. Golz
IPC分类号： H01L27/108 , G11C11/24 , G11C11/401 , G11C11/404 , H01L21/8242
CPC分类号： G11C11/404 , H01L27/108 , H01L27/10829
摘要： A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.
摘要翻译：描述了连接两个晶体管和一个电容器DRAM单元（1T DRAM单元）的两个晶体管和两个沟槽电容器（2T和2C DRAM单元）组成的双端口动态随机存取存储器（DRAM）单元。除了连接两个1T DRAM单元的两个存储节点的扩散连接之外，2T 2C DRAM和1T DRAM单元的掩模数据和横截面彼此完全兼容。这允许具有1T和1C DRAM单元的单端口存储器单元和具有2T和2C DRAM单元的双端口存储器单元被完全集成，形成真正的片上系统体系结构。或者，通过将电容器减半，随机存取写周期时间进一步降低，同时仍然保持数据保留时间。深沟槽加工时间也减少了沟槽深度的一半。

22. 发明授权

US06690198B2 Repeater with reduced power consumption 有权
标题翻译：中继器具有降低的功耗
公开(公告)号：US06690198B2
公开(公告)日：2004-02-10
申请号：US10114195
申请日：2002-04-02
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H03K190175
CPC分类号： H03K19/01721 , G11C7/1048 , G11C7/1069 , G11C11/4096 , H03K19/0013
摘要： A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.
摘要翻译：描述了具有改进的开关速度和降低的功耗的中继器电路。中继器电路被配置为从信号线的第一段接收输入信号，并且响应于主动控制信号将信号传递到信号线的第二段。

23. 发明授权

US06587388B2 Method and apparatus for reducing write operation time in dynamic random access memories 失效
公开(公告)号：US06587388B2
公开(公告)日：2003-07-01
申请号：US09844837
申请日：2001-04-27
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for preparing a dynamic random access memory (DRAM) cell for a write operation with a preset condition is disclosed. In an exemplary embodiment, the method includes creating a preset voltage level within the cell prior to a delayed write back in a destructive read architecture, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.

24. 发明授权

US6118726A Shared row decoder 失效
标题翻译：共享行解码器
公开(公告)号：US6118726A
公开(公告)日：2000-09-12
申请号：US17012
申请日：1998-02-02
申请人： L. Brian Ji , Toshiaki Kirihata
发明人： L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C11/407 , G11C8/10 , G11C11/401 , G11C11/409 , G11C8/00
CPC分类号： G11C8/10
摘要： A shared row decoder and shared row decoding method are disclosed herein which provides separate timed selection signals to each of a first memory unit and a second memory unit. The shared row decoder includes an address input circuit responsive to the states of a plurality of address signals and which provides an enabling or disabling input. In addition, first and second selection circuits are provided which are responsive to enabled conditions of first and second block selection inputs, first and second timing signals, respectively and enabling input of the address input circuit to provide separate timed selection signals to the first and second memory units, respectively.
摘要翻译：本文公开了共享行解码器和共享行解码方法，其向第一存储器单元和第二存储器单元中的每一个提供单独的定时选择信号。共享行解码器包括响应于多个地址信号的状态并且提供启用或禁用输入的地址输入电路。此外，提供了第一和第二选择电路，其分别响应于第一和第二块选择输入的使能条件，第一和第二定时信号，并使地址输入电路的输入能够向第一和第二选择信号提供单独的定时选择信号内存单元。

25. 发明授权

US06108798A Self programmed built in self test 失效
标题翻译：自编内建自检
公开(公告)号：US06108798A
公开(公告)日：2000-08-22
申请号：US887372
申请日：1997-07-02
申请人： David F. Heidel , Wei Hwang , Toshiaki Kirihata
发明人： David F. Heidel , Wei Hwang , Toshiaki Kirihata
IPC分类号： G01R31/28 , G06F11/27 , G06F13/26
CPC分类号： G11C29/16 , G11C29/028 , G11C29/56008 , G01R31/3187 , G11C2029/1208
摘要： A memory (e.g. , Dynamic Random Access Memory (DRAM)) with self-programmable Built In Self Test (BIST). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.
摘要翻译：具有自编程内置自检（BIST）的存储器（例如，动态随机存取存储器（DRAM））。可以是DRAM芯片的DRAM包括DRAM内核，微代码或初始命令ROM，BIST引擎，命令寄存器和自编程电路。在自检期间，BIST引擎可以正常测试DRAM，直到遇到错误。当遇到错误时，自编程电路在较不严格的条件下重新启动自检程序。可选地，当DRAM测试无错误时，自编程电路可以在更严格的条件下重新开始测试以确定DRAM功能限制。

26. 发明授权

US6002275A Single ended read write drive for memory 失效
标题翻译：用于内存的单端读写驱动器
公开(公告)号：US6002275A
公开(公告)日：1999-12-14
申请号：US17015
申请日：1998-02-02
申请人： Kohji Hosokawa , Toshiaki Kirihata
发明人： Kohji Hosokawa , Toshiaki Kirihata
IPC分类号： G11C11/409 , G11C8/10 , G11C11/401 , G11C7/02
CPC分类号： G11C8/10
摘要： A circuit and method are disclosed herein which convert signal values on first and second complementary outputs of a second sense amplifier to a single ended data signal for transmission on a read write drive (RWD) line. The circuit includes first and second followers coupled to the first and second complementary outputs, an inverter coupled to an output of the first follower, and a signal driver responsive to an output of the inverter and the second follower to drive signal levels on said RWD line between a first level representing a first data state and a second level representing a second data state.
摘要翻译：本文公开了一种电路和方法，其将第二读出放大器的第一和第二互补输出上的信号值转换为单端数据信号，以在读写驱动（RWD）线上传输。该电路包括耦合到第一和第二互补输出的第一和第二跟随器，耦合到第一跟随器的输出的反相器和响应于反相器和第二跟随器的输出的信号驱动器，以驱动所述RWD线上的信号电平在表示第一数据状态的第一电平和表示第二数据状态的第二电平之间。

27. 发明授权

US5831914A Variable size redundancy replacement architecture to make a memory fault-tolerant 失效
标题翻译：可变大小冗余替换体系结构，使内存容错
公开(公告)号：US5831914A
公开(公告)日：1998-11-03
申请号：US825949
申请日：1997-03-31
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/804 , G11C29/808
摘要： A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
摘要翻译：用于使存储器容错的可变大小冗余替换（VSRR）布置。支持存储器的冗余阵列包括多个可变大小的冗余单元，每个冗余单元包括多个冗余元件。用于修复存储器故障的冗余单元是独立控制的。维修单元内的所有冗余元件优选同时更换。冗余单元中的冗余元件通过解码地址线来控制。表征此配置的可变大小使得可以选择最有效的冗余单元，特别是最接近要替换的故障群集大小的冗余单元。这种配置可显着降低由添加的冗余元件和控制电路产生的开销，同时提高访问速度并降低功耗。最后，由优先级解码器控制的容错块冗余使得可以使用VSRR单元来修复块冗余中的故障，在其用于替换存储器内的有缺陷块之前。

28. 发明授权

US5831912A Semiconductor memory having space-efficient layout 失效
标题翻译：半导体存储器具有节省空间的布局
公开(公告)号：US5831912A
公开(公告)日：1998-11-03
申请号：US938074
申请日：1997-09-26
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C11/401 , G11C5/02 , G11C7/18 , G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C7/00 , G11C7/02
CPC分类号： G11C5/025 , G11C11/4097 , G11C7/18
摘要： The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.
摘要翻译：本公开包括具有空间有效布局的半导体存储器。动态随机存取存储器（DRAM）芯片具有以行和列排列的多个存储单元（18）。半导体存储器包括设置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中每个读出放大器（14）设置在相关联的列（16）的读出放大器区域中，。多个放大器（124或126）由至少一个驱动器（140或142）驱动，多个放大器中的每个放大器设置在一对互补位线（120）之间并位于读出放大器区域内。至少一个驱动器至少与至少一个驱动器共享至少一个横向于列方向延伸的扩散区域，使得读出放大器组的触点数量减少。

29. 发明授权

US5610867A DRAM signal margin test method 失效
标题翻译： DRAM信号余量测试方法
公开(公告)号：US5610867A
公开(公告)日：1997-03-11
申请号：US535446
申请日：1995-09-28
申请人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4091 , G11C29/50 , G06F2201/81 , G11C11/401
摘要： In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.
摘要翻译：在本发明的优选实施例中，位线对通过一对高电阻通过门耦合到感测放大器。在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对之一。因此，数据从感测放大器传递到第二读出放大器和芯片外。数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。此外，由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。代替检测放大器参考电压，如现有技术的信号余量测试，通过改变单元信号来测试单元信号余量。可以选择VS来确定高和低信号余量。

30. 发明授权

US5561630A Data sense circuit for dynamic random access memories 失效
标题翻译：用于动态随机存取存储器的数据检测电路
公开(公告)号：US5561630A
公开(公告)日：1996-10-01
申请号：US535704
申请日：1995-09-28
申请人： Daisuke Katoh , Toshiaki Kirihata , Munehiro Yoshida
发明人： Daisuke Katoh , Toshiaki Kirihata , Munehiro Yoshida
IPC分类号： G11C11/409 , G11C7/10 , G11C11/4091 , G11C11/4094 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4094 , G11C11/4091 , G11C7/1006 , G11C2207/002 , G11C2207/005
摘要： An improved data sense for a DRAM. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.
摘要翻译：改进了DRAM的数据检测。每个位线对通过一对高电阻通过门耦合到感测放大器。在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对中的一个。因此，数据从感测放大器传递到第二读出放大器和芯片外。数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。

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