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21. 发明授权

US09106625B2 Two parallel engines for high speed transmit IPSEC processing 有权
标题翻译：两个并行引擎，用于高速传输IPSEC处理
公开(公告)号：US09106625B2
公开(公告)日：2015-08-11
申请号：US12625086
申请日：2009-11-24
申请人： Marufa Kaniz , Jeffrey Dwork , Robert Alan Williams , Mohammad Y. Maniar , Somnath Viswanath
发明人： Marufa Kaniz , Jeffrey Dwork , Robert Alan Williams , Mohammad Y. Maniar , Somnath Viswanath
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L63/164
摘要： The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.
摘要翻译：本发明涉及一种用于将主机系统与网络进行接口的网络接口系统。网络接口系统包括总线接口系统，媒体访问控制系统和安全系统。网络接口从主机处理器卸载IPsec处理。根据本发明，安全系统包括用于加密和认证输出数据的两个处理器。输出数据分组被交替地发送到一个或另一个处理器，由此相对于接收处理可以加速传输处理。

22. 发明授权

US08009584B1 System and method for implementing an IRC across multiple network devices 有权
标题翻译：跨多个网络设备实现IRC的系统和方法
公开(公告)号：US08009584B1
公开(公告)日：2011-08-30
申请号：US09877120
申请日：2001-06-11
申请人： Somnath Viswanath , Marufa Kaniz
发明人： Somnath Viswanath , Marufa Kaniz
IPC分类号： H04L12/28
CPC分类号： H04L49/552 , H04L49/351
摘要： A system includes a plurality of network devices and an external memory. Each network device includes an address table. The external memory includes a group of address tables corresponding to the address tables of the network devices. The system monitors the address table associated with each of the network devices, detects whether one of the address tables has been updated, and updates the corresponding address table in the external memory in response to detecting an update to one of the address tables.
摘要翻译：系统包括多个网络设备和外部存储器。每个网络设备包括一个地址表。外部存储器包括与网络设备的地址表相对应的一组地址表。系统监视与每个网络设备相关联的地址表，检测地址表是否已被更新，并且响应于检测到对其中一个地址表的更新而更新外部存储器中的相应地址表。

23. 发明授权

US07412726B1 Method and apparatus for out of order writing of status fields for receive IPsec processing 有权
标题翻译：用于接收IPsec处理的状态字段无序写入的方法和装置
公开(公告)号：US07412726B1
公开(公告)日：2008-08-12
申请号：US10730621
申请日：2003-12-08
申请人： Somnath Viswanath
发明人： Somnath Viswanath
IPC分类号： G06F7/04
CPC分类号： H04L63/0272 , H04L63/0485 , H04L63/164
摘要： Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, where the network interface system may be fabricated as a single integrated circuit chip. Systems and methods are disclosed wherein out-of-order writing is used to improve throughput for the security system on the receive end.
摘要翻译：公开了一种网络接口系统，包括总线接口系统，媒体访问控制系统，存储系统，用于选择性地加密输出数据和解密输入数据的安全系统，其中网络接口系统可被制造为单个集成电路芯片。公开了系统和方法，其中使用无序写入来提高接收端上的安全系统的吞吐量。

24. 发明授权

US07099325B1 Alternately accessed parallel lookup tables for locating information in a packet switched network 有权
标题翻译：用于在分组交换网络中定位信息的可选择的并行查找表
公开(公告)号：US07099325B1
公开(公告)日：2006-08-29
申请号：US09851934
申请日：2001-05-10
申请人： Marufa Kaniz , Somnath Viswanath
发明人： Marufa Kaniz , Somnath Viswanath
IPC分类号： H04L12/56
CPC分类号： H04L29/12009 , H04L45/745 , H04L49/15 , H04L49/3009 , H04L49/351 , H04L61/00 , H04L69/22
摘要： An address lookup table in a multiport switch is implemented as a plurality of address sub-tables. Entries in the address sub-tables are stored at row addresses based on a hash of the information in the entry. Hash collisions are stored in a common heap as a linked list of chained values. Entries in the address sub-tables at any particular address are alternated between the address sub-tables. A search of the address sub-table for the particular entry is performed simultaneously on the plurality of address sub-tables. In this manner, the total memory size of the address table can be increased relative to a single address sub-table while decreasing the length of the longest chain length and the length of the average chain length.
摘要翻译：多端口交换机中的地址查找表被实现为多个地址子表。地址子表中的条目基于条目中信息的散列值存储在行地址中。哈希冲突作为链接值的链表存储在公共堆中。任何地址子表中的地址子表中的条目在地址子表之间交替。在多个地址子表上同时执行特定条目的地址子表的搜索。以这种方式，可以相对于单个地址子表增加地址表的总存储器大小，同时减少最长链长度和平均链长度的长度。

25. 发明授权

US06963566B1 Multiple address lookup engines running in parallel in a switch for a packet-switched network 失效
标题翻译：用于分组交换网络的交换机中并行运行的多个地址查找引擎
公开(公告)号：US06963566B1
公开(公告)日：2005-11-08
申请号：US09851935
申请日：2001-05-10
申请人： Marufa Kaniz , Somnath Viswanath
发明人： Marufa Kaniz , Somnath Viswanath
IPC分类号： H04L12/56
CPC分类号： H04L45/745 , H04L49/3009 , H04L49/351
摘要： A multiport device includes an internal rules checking (IRC) circuit that makes frame forwarding decisions for frames received from a network. The IRC circuit includes multiple frame lookup components implemented in parallel. More particularly, each of the multiple frame lookup components includes a source address lookup component and a destination address lookup component, and an address table. The source address lookup component and the destination address lookup component accesses the address table to determine the correct forwarding information for a frame. If an address is not present in the table, a source address learning component updates the table. The source address learning component may be shared by each of the multiple frame lookup components.
摘要翻译：多端口设备包括对从网络接收的帧进行帧转发决定的内部规则检查（IRC）电路。 IRC电路包括并行实现的多个帧查找组件。更具体地，多个帧查找组件中的每一个包括源地址查找组件和目的地地址查找组件以及地址表。源地址查找组件和目的地址查找组件访问地址表以确定帧的正确转发信息。如果表中不存在地址，源地址学习组件将更新表。源地址学习组件可以被多个帧查找组件中的每一个共享。

26. 发明授权

US06128310A Multiport data network switch having a random number generator shared by multiple media access controllers 失效
标题翻译：具有由多个媒体接入控制器共享的随机数发生器的多端口数据网络交换机
公开(公告)号：US06128310A
公开(公告)日：2000-10-03
申请号：US993780
申请日：1997-12-18
申请人： Peter Ka-Fai Chow , Somnath Viswanath
发明人： Peter Ka-Fai Chow , Somnath Viswanath
IPC分类号： H04L13/08 , G06F11/26 , G06F12/00 , G06F13/00 , G06F13/10 , G06F13/16 , G06F13/24 , G06F15/00 , G06F15/16 , G08B5/00 , G11C11/412 , H04B7/14 , H04J3/02 , H04J3/12 , H04J3/22 , H04J3/24 , H04L12/18 , H04L12/24 , H04L12/28 , H04L12/413 , H04L12/44 , H04L12/46 , H04L12/50 , H04L12/54 , H04L12/66 , H04L12/861 , H04L12/863 , H04L12/879 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L12/939 , H04L12/947 , H04Q3/545 , H04Q11/00
CPC分类号： H04L49/3009 , G06F13/1605 , G06F13/24 , G11C11/412 , H04L12/4641 , H04L12/5693 , H04L41/0213 , H04L47/6225 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/255 , H04L49/30 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/50 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9063 , H04L49/9073 , H04L49/9078 , H04L49/9084 , H04Q3/54591 , H04L12/1863 , H04L12/4645 , H04L12/467 , H04L49/3054 , H04L49/40 , H04Q2213/1316 , H04Q2213/13162
摘要： A multiport data network switch with each port associated with a media access controller (MAC) that is allocated a time slot in a repetitive sequence of clock cycles. A random number generator is coupled in common to each MAC to output a random number signal thereto. In response to a collision indicating signal, received at a port during a data transmission, the MAC outputs a retransmission retry signal in accordance with the random number signal that represents a number of delay cycles in which said transmission is delayed. The random number signal generator outputs an increasing multibit signal that is periodically reset. The MAC associated with each port is coupled in common to the shared random number signal generator and gains access thereto at a different respective time slot.
摘要翻译：多端口数据网络交换机，每个端口与媒体接入控制器（MAC）相关联，媒体接入控制器（MAC）以时钟周期的重复序列分配时隙。随机数发生器共同耦合到每个MAC以向其输出随机数信号。响应于在数据传输期间在端口接收到的冲突指示信号，MAC根据表示所述传输被延迟的延迟周期数的随机数信号输出重传重试信号。随机数信号发生器输出周期性复位的增加的多位信号。与每个端口相关联的MAC被共同耦合到共享随机数信号发生器，并在不同的相应时隙获得对其的访问。

27. 发明授权

US6080203A Apparatus and method for designing a test and modeling system for a network switch device 失效
标题翻译：用于设计网络交换机设备的测试和建模系统的装置和方法
公开(公告)号：US6080203A
公开(公告)日：2000-06-27
申请号：US992798
申请日：1997-12-18
申请人： Charles Akum Njinda , Somnath Viswanath
发明人： Charles Akum Njinda , Somnath Viswanath
IPC分类号： G01R31/3185 , G06F17/50
CPC分类号： G01R31/318591
摘要： An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.
摘要翻译：用于设计测试建模系统的布置提供了测试层级，其中具有内部存储器和逻辑结构的非标准设备元件通过将设备元件划分成可识别存储器模型和与存储器模型分离的可识别逻辑模型来建模。然后使用现有的设计和仿真工具，并与现有的硬件实现进行比较，验证隔离模型的准确性。一旦修正的模型已经被验证，新的模型可以存储在模型库中以供将来使用。

28. 发明授权

US08351445B1 Network interface systems and methods for offloading segmentation and/or checksumming with security processing 有权
标题翻译：用于通过安全处理卸载分段和/或校验和的网络接口系统和方法
公开(公告)号：US08351445B1
公开(公告)日：2013-01-08
申请号：US10870318
申请日：2004-06-17
申请人： Marufa Kaniz , Jeffrey Dwork , Chin-Wei Kate Liang , Kevin Pond, legal representative , Somnath Viswanath , Robert Alan Williams
发明人： Marufa Kaniz , Jeffrey Dwork , Chin-Wei Kate Liang , Somnath Viswanath , Robert Alan Williams
IPC分类号： H04J3/00 , H04L12/50 , H04Q11/00
CPC分类号： H04L9/0643 , H04L9/0637 , H04L63/164 , H04L2209/125 , H04L2209/20
摘要： Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, a checksum system for generating and verifying checksum values, and a segmentation system for selectively segmenting outgoing data, where the network interface system may be fabricated as a single integrated circuit chip. Methods are also provided for interfacing a host system with a network, in which checksum information is obtained from the host system, which is used to generate checksum values for outgoing data while the data is being stored in a network interface memory system.
摘要翻译：公开了一种网络接口系统，包括总线接口系统，媒体访问控制系统，存储系统，用于选择性地加密输出数据和解密输入数据的安全系统，用于生成和验证校验和值的校验和系统，以及用于选择性地分段输出数据，其中网络接口系统可以被制造为单个集成电路芯片。还提供了用于将主机系统与网络连接的方法，其中从主机系统获得校验和信息，其用于在将数据存储在网络接口存储器系统中时产生用于输出数据的校验和值。

29. 发明授权

US07685434B2 Two parallel engines for high speed transmit IPsec processing 有权
标题翻译：两个并行引擎，用于高速传输IPsec处理
公开(公告)号：US07685434B2
公开(公告)日：2010-03-23
申请号：US10791557
申请日：2004-03-02
申请人： Marufa Kaniz , Jeffrey Dwork , Robert Alan Williams , Mohammad Y. Maniar , Somnath Viswanath
发明人： Marufa Kaniz , Jeffrey Dwork , Robert Alan Williams , Mohammad Y. Maniar , Somnath Viswanath
IPC分类号： G06F21/00 , G06F11/30
CPC分类号： H04L63/0485 , H04L63/164
摘要： The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.
摘要翻译：本发明涉及一种用于将主机系统与网络进行接口的网络接口系统。网络接口系统包括总线接口系统，媒体访问控制系统和安全系统。网络接口从主机处理器卸载IPsec处理。根据本发明，安全系统包括用于加密和认证输出数据的两个处理器。输出数据分组被交替地发送到一个或另一个处理器，由此相对于接收处理可以加速传输处理。

30. 发明授权

US07016352B1 Address modification within a switching device in a packet-switched network 有权
标题翻译：在分组交换网络中的交换设备内的地址修改
公开(公告)号：US07016352B1
公开(公告)日：2006-03-21
申请号：US09814811
申请日：2001-03-23
申请人： Peter Ka-Fai Chow , Somnath Viswanath , Shr-Jie Tzeng
发明人： Peter Ka-Fai Chow , Somnath Viswanath , Shr-Jie Tzeng
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/604 , H04L49/205 , H04L49/3009
摘要： A multiport switching device includes an Internal Rules Checker (IRC) that determines forwarding addresses for packets received at the device. The determined forwarding addresses may include a new MAC destination address that is to substituted for the MAC destination address of the received packet. In one implementation, the new MAC destination address is transmitted from the IRC to the dequeuing logic by transmitting pairs of adjacent words through the switch output queues. In other implementations, the new MAC destination address is transmitted from the IRC to the dequeuing logic by transmitting an index field to the output queuing logic or by having the IRC write the new MAC destination address directly to memory.
摘要翻译：多端口交换设备包括内部规则检查器（IRC），其确定在设备处接收的分组的转发地址。所确定的转发地址可以包括将替换接收到的分组的MAC目的地地址的新的MAC目的地址。在一个实现中，新的MAC目的地地址通过交换机输出队列中的相邻字对来从IRC发送到出队逻辑。在其他实现中，通过向输出排队逻辑发送索引字段或通过使IRC将新的MAC目的地址直接写入存储器，将新的MAC目的地地址从IRC发送到出队逻辑。

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