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21. 发明申请

US20120056259A1 MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL 有权
标题翻译：存储器单元，存储器件和用于制造存储器单元的方法
公开(公告)号：US20120056259A1
公开(公告)日：2012-03-08
申请号：US12877284
申请日：2010-09-08
申请人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
发明人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
IPC分类号： H01L29/68 , H01L21/762
CPC分类号： H01L21/76232 , H01L27/11568 , H01L29/792
摘要： A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.
摘要翻译：提供了包括基板，堆叠栅极结构和第一隔离结构的存储单元。衬底具有位于第一掺杂区域和第二掺杂区域之间的第一掺杂区域，第二掺杂区域和沟道区域。堆叠的栅极结构设置在沟道上，并且至少包括电荷捕获层和从底部到顶部的栅极。第一隔离结构设置在衬底中并连接到第一掺杂区并从第一掺杂区向下延伸预定长度，第一隔离结构的底部低于第一掺杂区的底部。

22. 发明授权

US08476694B2 Memory cell, memory device and method for manufacturing memory cell 有权
标题翻译：存储单元，存储器件和用于制造存储单元的方法
公开(公告)号：US08476694B2
公开(公告)日：2013-07-02
申请号：US12877284
申请日：2010-09-08
申请人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
发明人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/76232 , H01L27/11568 , H01L29/792
摘要： A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.
摘要翻译：提供了包括基板，堆叠栅极结构和第一隔离结构的存储单元。衬底具有位于第一掺杂区域和第二掺杂区域之间的第一掺杂区域，第二掺杂区域和沟道区域。堆叠的栅极结构设置在沟道上，并且至少包括电荷捕获层和从底部到顶部的栅极。第一隔离结构设置在衬底中并连接到第一掺杂区并从第一掺杂区向下延伸预定长度，第一隔离结构的底部低于第一掺杂区的底部。

23. 发明申请

US20120236649A1 HOT CARRIER PROGRAMMING OF NAND FLASH MEMORY 审中-公开
标题翻译： NAND FLASH存储器的热载波编程
公开(公告)号：US20120236649A1
公开(公告)日：2012-09-20
申请号：US13050658
申请日：2011-03-17
申请人： Shaw-Hung Ku , I-Chen Yang
发明人： Shaw-Hung Ku , I-Chen Yang
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A NAND memory device includes strings of NAND memory cells, where each memory cell includes a charge trapping structure formed over a lightly-doped substrate region. A selected one of the NAND memory cells can be programmed by application of a relatively low program voltage in combination with a previously-applied set-up voltage, which is applied to the substrate for initiating inversion. The inversion in the substrate causes electrons to become hot in the channel regions, including the channel of the selected memory cell. As a result, the relatively lower program voltage can be used at the control gate of the selected memory cell for sufficiently energizing hot electrons to tunnel into the charge trapping structure of the selected memory cell.
摘要翻译： NAND存储器件包括NAND存储器单元串，其中每个存储器单元包括在轻掺杂衬底区域上形成的电荷俘获结构。可以通过将相对较低的编程电压与预先施加的建立电压结合使用来编程所选择的一个NAND存储器单元，该电压施加到用于启动反转的衬底。衬底中的反转导致电子在包括所选择的存储单元的通道的通道区域中变热。结果，可以在所选择的存储单元的控制栅极处使用相对较低的编程电压，以充分激励热电子以隧道进入所选存储单元的电荷捕获结构。

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