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21. 发明授权

US08211758B2 Semiconductor device and method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08211758B2
公开(公告)日：2012-07-03
申请号：US12699611
申请日：2010-02-03
申请人： Fujio Masuoka , Shintaro Arai , Hiroki Nakamura , Tomohiko Kudo
发明人： Fujio Masuoka , Shintaro Arai , Hiroki Nakamura , Tomohiko Kudo
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78642 , H01L29/42392 , H01L29/66772
摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.
摘要翻译：本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

22. 发明申请

US20110303985A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110303985A1
公开(公告)日：2011-12-15
申请号：US13113482
申请日：2011-05-23
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Yu Jiang , King-Jien Chui , Yisuo Li , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Yu Jiang , King-Jien Chui , Yisuo Li , Xiang Li , Zhixian Chen , Nansheng Shen , Vladimir Bliznetsov , Kavitha Devi Buddharaju , Navab Singh
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66484 , H01L21/823885 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.
摘要翻译：半导体器件包括：平面硅层上的柱状硅层; 形成在柱状硅层的底部区域中的第一n +型硅层; 形成在柱状硅层的上部区域的第二n +型硅层; 栅极绝缘膜，形成在第一和第二n +型硅层之间的沟道区的周边; 栅电极，形成在所述栅极绝缘膜的周边，并具有第一金属 - 硅化合物层; 形成在栅电极和平面硅层之间的绝缘膜，形成在柱状硅层的上侧壁中的绝缘膜侧壁; 形成在所述平面硅层中的第二金属 - 硅化合物层; 以及形成在第二n +型硅层上的电接触。

23. 发明申请

US20100301402A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100301402A1
公开(公告)日：2010-12-02
申请号：US12787929
申请日：2010-05-26
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/42356 , H01L29/42392 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/78618 , H01L29/78642
摘要： Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar.
摘要翻译：提供了能够防止由于泄漏电流的增加而导致的SGT（即三维半导体晶体管）的功耗的增加的半导体器件。半导体器件包括：第一导电型第一硅柱：围绕第一硅柱的侧表面的第一电介质; 围绕电介质的栅极; 设置在第一硅柱下方的第二硅柱; 以及设置在第一硅柱的顶部上的第三硅柱。第二硅柱具有形成在其表面上的第二导电型高浓度杂质区，除了与第一硅柱的接触表面区域的至少一部分以及形成在其中的第一导电型杂质区域第二导电型高浓度杂质区。第三硅柱具有形成在其表面上的第二导电型高浓度杂质区域，除了与第一硅柱的接触表面区域的至少一部分以及形成在其中的第一导电型杂质区域第三硅柱的第二导电型高浓度杂质区。第二硅柱和第三硅柱中的每一个的第一导电型杂质区的长度大于从相应的一个的第二导电型杂质区的第二导电型高浓度杂质区的基极部延伸的耗尽层的长度第二硅柱和第三硅柱。

24. 发明申请

US20100264485A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100264485A1
公开(公告)日：2010-10-21
申请号：US12761735
申请日：2010-04-16
申请人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
发明人： Fujio Masuoka , Hiroki Nakamura , Shintaro Arai , Tomohiko Kudo , Navab Singh , Kavitha Devi Buddharaju , Shen Nansheng , Rukmani Devi Sayanthan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/42392 , H01L29/458 , H01L29/66666 , H01L29/78642
摘要： This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type.
摘要翻译：本发明提供一种制造半导体器件的方法，其包括以下步骤：在第一平坦半导体层上形成第一柱状半导体层; 在所述第一柱状半导体层的下部形成第二导电类型的第一半导体层; 在所述第一柱状硅层的下侧壁周围形成第一绝缘膜; 在第一柱状硅层周围形成栅极绝缘膜和栅电极; 形成侧壁形状的第二绝缘膜以围绕所述第一柱状硅层的上侧壁; 在第二导电类型的第一半导体层和第二导电类型的第二半导体层之间形成第一导电类型的半导体层; 以及在所述第二导电类型的所述第一半导体层的上表面上形成金属 - 半导体化合物。

25. 发明申请

US20100210079A1 PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的生产方法
公开(公告)号：US20100210079A1
公开(公告)日：2010-08-19
申请号：US12704004
申请日：2010-02-11
申请人： Fujio Masuoka , Tomohiko Kudo , Shintaro Arai , Hiroki Nakamura
发明人： Fujio Masuoka , Tomohiko Kudo , Shintaro Arai , Hiroki Nakamura
IPC分类号： H01L21/336
CPC分类号： H01L29/78642 , H01L29/42392 , H01L29/66666
摘要： It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode.
摘要翻译：旨在提供一种能够获得用于降低源极，漏极和栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及要获得的柱状半导体的期望直径的结构的SGT制造方法。该方法包括以下步骤：形成柱状第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极电极的顶部接触的第一电介质膜，通过栅极电介质膜形成; 在所述栅电极的侧壁上形成第一电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层的上部和下方的每个第二导电型半导体层上形成金属 - 半导体化合物; 去除伪栅极电介质膜和伪栅电极并形成高k栅极电介质膜和金属栅电极。

26. 发明申请

US20100207200A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100207200A1
公开(公告)日：2010-08-19
申请号：US12704306
申请日：2010-02-11
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/78
CPC分类号： H01L29/42356 , H01L29/0657 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/7827
摘要： It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region (510) formed in a part of a first-conductive type semiconductor substrate (100), a first silicon pillar (810) of an arbitrary cross-sectional shape formed on the second-conductive type impurity region, a first insulating body (310) surrounding a part of a surface of the first silicon pillar, a gate (210) surrounding the first insulating body, and a second silicon pillar (820) which is formed on the first silicon pillar and which includes a second-conductive type impurity region (540). The gate is disposed to be separated from the semiconductor substrate by a second insulating body and is disposed to be separated from the second silicon pillar by the second insulating body. The capacitance between the gate and the semiconductor substrate is less than a gate capacitance, and the capacitance between the gate and the second silicon pillar is less than the gate capacitance.
摘要翻译：旨在解决由于作为三维半导体器件的周围栅晶体管（SGT）的寄生电容的增加而导致的功耗增加和操作速度的降低的问题，以提供实现增加速度的SGT 半导体电路的功耗降低。半导体器件包括形成在第一导电型半导体衬底（100）的一部分中的第二导电型杂质区（510），形成在第二导电类型半导体衬底上的任意截面形状的第一硅柱（810）围绕第一硅柱的表面的一部分的第一绝缘体（310），围绕第一绝缘体的栅极（210）和形成在第一硅柱上的第二硅柱（820）并且其包括第二导电型杂质区（540）。栅极被设置成通过第二绝缘体与半导体衬底分离，并且被设置成通过第二绝缘体与第二硅柱分离。栅极和半导体衬底之间的电容小于栅极电容，并且栅极和第二硅柱之间的电容小于栅极电容。

27. 发明授权

US08772881B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08772881B2
公开(公告)日：2014-07-08
申请号：US12794088
申请日：2010-06-04
申请人： Fujio Masuoka , Hiroki Nakamura
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L27/11 , H01L27/088
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged underneath the first arc-shaped semiconductor layer.
摘要翻译：提供高度集成的基于SGT的SRAM的目的是通过使用逆变器形成SRAM来实现，该逆变器包括第一岛状半导体层，与第一岛状半导体层的周边接触的第一栅极电介质膜，具有与第一栅极电介质膜接触的一个表面的第一栅极电极，与第一栅电极的另一表面接触的第二栅极电介质膜，与第二栅极电介质膜接触的第一弧形半导体层，第一栅极电极布置在第一岛状半导体层的顶部上的第一导电型高浓度半导体层，布置在第一岛状半导体层下方的第二第一导电型高浓度半导体层，第一导电型高浓度半导体层，第一导电型高浓度半导体层，布置在第一弧形半导体层的顶部上的高浓度半导体层和第二第二导电型高浓度半导体层所述半导体层布置在所述第一弧形半导体层下方。

28. 发明授权

US08564034B2 Solid-state imaging device 有权
标题翻译：固态成像装置
公开(公告)号：US08564034B2
公开(公告)日：2013-10-22
申请号：US13606823
申请日：2012-09-07
申请人： Fujio Masuoka , Nozomu Harada
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L31/062
CPC分类号： H01L27/14616 , H01L27/14614
摘要： In a solid-state imaging device, a pixel has a first island-shaped semiconductor (P11) formed on a substrate (1) and a drive output circuit has second island-shaped semiconductors (4a to 4c) formed on the substrate at the same height as that of the first island-shaped semiconductor (P11). The first island-shaped semiconductor (P11) has a first gate insulating layer (6b) formed on an outer periphery thereof and a first gate conductor layer (105a) surrounding the first gate insulating layer (6b). The second island-shaped semiconductors (4a to 4c) have a second gate insulating layer (6a) formed on an outer periphery thereof and a second gate conductor layer (7a) surrounding the second gate insulating layer (6a). The first gate conductor layer (105a) and the second gate conductor layer (7a) have bottom portions located on the same plane.
摘要翻译：在固态成像装置中，像素具有形成在基板（1）上的第一岛状半导体（P11），驱动输出电路具有形成在基板上的第二岛状半导体（4a〜4c）高度为第一岛状半导体（P11）的高度。第一岛状半导体（P11）具有形成在其外周上的第一栅极绝缘层（6b）和围绕第一栅极绝缘层（6b）的第一栅极导体层（105a）。第二岛状半导体（4a〜4c）具有在其外周形成的第二栅极绝缘层（6a）和围绕第二栅极绝缘层（6a）的第二栅极导体层（7a）。第一栅极导体层（105a）和第二栅极导体层（7a）具有位于同一平面上的底部。

29. 发明授权

US08558317B2 Semiconductor device and production method 有权
公开(公告)号：US08558317B2
公开(公告)日：2013-10-15
申请号：US12854564
申请日：2010-08-11
申请人： Fujio Masuoka , Hiroki Nakamura
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L27/092
CPC分类号： H01L21/823885 , H01L21/8238 , H01L21/823807 , H01L21/823857 , H01L21/84 , H01L27/092 , H01L27/12
摘要： The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer.

30. 发明授权

US08476699B2 Method for producing semiconductor device and semiconductor device 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08476699B2
公开(公告)日：2013-07-02
申请号：US13414039
申请日：2012-03-07
申请人： Fujio Masuoka , Nozomu Harada
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L29/66 , H01L31/062 , H01L27/14 , H01L31/06 , H01L27/108 , H01L21/00 , H01L21/46 , H01L21/461
CPC分类号： H01L21/823487 , H01L21/823885 , H01L27/0629 , H01L27/088 , H01L27/092 , H01L27/14612 , H01L27/14632 , H01L27/14643 , H01L27/14687 , H01L27/14689 , H01L29/6609 , H01L29/66666 , H01L29/66909 , H01L29/7827 , H01L29/8083 , H01L29/8613
摘要： A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused.
摘要翻译：一种制造半导体器件的方法包括在第一半导体衬底上形成导体层和含有施主杂质或受主杂质的第一半导体层的步骤; 形成第二绝缘层以覆盖第一半导体层的步骤; 将第一半导体衬底细化为预定厚度的步骤; 从所述第一半导体基板形成在所述第一半导体层上具有柱状结构的柱状半导体的工序; 通过从第一半导体层扩散杂质而在柱状半导体中形成第一半导体区域的步骤; 以及用杂质扩散到其中的柱状半导体形成固态成像装置的像素的步骤。

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