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21. 发明申请

US20110115011A1 SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体元件和半导体器件
公开(公告)号：US20110115011A1
公开(公告)日：2011-05-19
申请号：US12944310
申请日：2010-11-11
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/823431 , H01L29/0657 , H01L29/42356 , H01L29/42364 , H01L29/42372 , H01L29/42392 , H01L29/66666 , H01L29/78642
摘要： The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region.
摘要翻译：本发明的目的是提供通过增加SGT的导通电流来实现作为三维半导体的周围栅极晶体管（SGT）的高速操作的半导体器件。该目的通过提供一种半导体元件来实现，其中源极，漏极和栅极分层地定位在衬底上，半导体元件设置有硅柱; 围绕所述硅柱的侧表面的绝缘体; 围绕绝缘体的门; 位于硅柱上方或下方的源区; 以及位于硅柱下方或上方的漏极区域; 其中所述硅柱与所述源极区域的接触表面小于所述硅柱与所述漏极区的接触表面。

22. 发明授权

US08901640B2 Semiconductor element and semiconductor device 有权
标题翻译：半导体元件和半导体器件
公开(公告)号：US08901640B2
公开(公告)日：2014-12-02
申请号：US12944310
申请日：2010-11-11
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/7827 , H01L21/823431 , H01L29/0657 , H01L29/42356 , H01L29/42364 , H01L29/42372 , H01L29/42392 , H01L29/66666 , H01L29/78642
摘要： The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region.
摘要翻译：本发明的目的是通过增加SGT的导通电流来提供实现作为三维半导体的周围栅极晶体管（SGT）的高速操作的半导体器件。该目的通过提供一种半导体元件来实现，其中源极，漏极和栅极分层地定位在衬底上，半导体元件设置有硅柱; 围绕所述硅柱的侧表面的绝缘体; 围绕绝缘体的门; 位于硅柱上方或下方的源区; 以及位于硅柱下方或上方的漏极区域; 其中所述硅柱与所述源极区域的接触表面小于所述硅柱与所述漏极区的接触表面。

23. 发明申请

US20100187601A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100187601A1
公开(公告)日：2010-07-29
申请号：US12699626
申请日：2010-02-03
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L29/0657 , H01L29/41741 , H01L29/42356 , H01L29/42372 , H01L29/456
摘要： A hermetic compressor includes a closed vessel for storing lubricating oil, an electric-driving element, and a compressing element driven by the electric-driving element. The compressing element includes a cylinder block forming a compression chamber, a piton that reciprocates inside the compression chamber, and an oiling device for supplying the lubricating oil to an outer circumference of the piston. A first oil groove is concavely formed on the outer circumference of the piston, and a second oil groove is concavely formed on a side opposite to the compression chamber relative to the first oil groove. The second oil groove has a spatial volume same or greater than that of the first oil groove. An expanded clearance portion is provided such that a clearance between the piston and the cylindrical hole portion broadens from a top dead point to a bottom dead point.
摘要翻译：封闭式压缩机包括用于存储润滑油的密闭容器，电驱动元件和由电驱动元件驱动的压缩元件。压缩元件包括形成压缩室的气缸体，在压缩室内往复运动的立柱，以及用于将润滑油供给到活塞的外周的供油装置。第一油槽凹入地形成在活塞的外周上，并且第二油槽相对于第一油槽在与压缩室相对的一侧凹入地形成。第二油槽具有与第一油槽相同或更大的空间体积。设置有扩大的间隙部分，使得活塞和圆柱形孔部之间的间隙从上死点扩大到下死点。

24. 发明授权

US08896056B2 Surrounding gate transistor semiconductor device 有权
标题翻译：周边栅晶体管半导体器件
公开(公告)号：US08896056B2
公开(公告)日：2014-11-25
申请号：US12704306
申请日：2010-02-11
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/49 , H01L29/51
CPC分类号： H01L29/42356 , H01L29/0657 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/7827
摘要： It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region (510) formed in a part of a first-conductive type semiconductor substrate (100), a first silicon pillar (810) of an arbitrary cross-sectional shape formed on the second-conductive type impurity region, a first insulating body (310) surrounding a part of a surface of the first silicon pillar, a gate (210) surrounding the first insulating body, and a second silicon pillar (820) which is formed on the first silicon pillar and which includes a second-conductive type impurity region (540). The gate is disposed to be separated from the semiconductor substrate by a second insulating body and is disposed to be separated from the second silicon pillar by the second insulating body. The capacitance between the gate and the semiconductor substrate is less than a gate capacitance, and the capacitance between the gate and the second silicon pillar is less than the gate capacitance.
摘要翻译：旨在解决由于作为三维半导体器件的周围栅晶体管（SGT）的寄生电容的增加而导致的功耗增加和操作速度的降低的问题，以提供实现增加速度的SGT 半导体电路的功耗降低。半导体器件包括形成在第一导电型半导体衬底（100）的一部分中的第二导电型杂质区（510），形成在第二导电类型半导体衬底上的任意截面形状的第一硅柱（810）围绕第一硅柱的表面的一部分的第一绝缘体（310），围绕第一绝缘体的栅极（210）和形成在第一硅柱上的第二硅柱（820）并且其包括第二导电型杂质区（540）。栅极被设置成通过第二绝缘体与半导体衬底分离，并且被设置成通过第二绝缘体与第二硅柱分离。栅极和半导体衬底之间的电容小于栅极电容，并且栅极和第二硅柱之间的电容小于栅极电容。

25. 发明授权

US08502303B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08502303B2
公开(公告)日：2013-08-06
申请号：US12787929
申请日：2010-05-26
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/42356 , H01L29/42392 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/78618 , H01L29/78642
摘要： Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar.
摘要翻译：提供了能够防止由于泄漏电流的增加而导致的SGT（即三维半导体晶体管）的功耗的增加的半导体器件。半导体器件包括：第一导电型第一硅柱：围绕第一硅柱的侧表面的第一电介质; 围绕电介质的栅极; 设置在第一硅柱下方的第二硅柱; 以及设置在第一硅柱的顶部上的第三硅柱。第二硅柱具有形成在其表面上的第二导电型高浓度杂质区，除了与第一硅柱的接触表面区域的至少一部分以及形成在其中的第一导电型杂质区域第二导电型高浓度杂质区。第三硅柱具有形成在其表面上的第二导电型高浓度杂质区域，除了与第一硅柱的接触表面区域的至少一部分以及形成在其中的第一导电型杂质区域第三硅柱的第二导电型高浓度杂质区。第二硅柱和第三硅柱中的每一个的第一导电型杂质区的长度大于从相应的一个的第二导电型杂质区的第二导电型高浓度杂质区的基极部延伸的耗尽层的长度第二硅柱和第三硅柱。

26. 发明申请

US20100301402A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100301402A1
公开(公告)日：2010-12-02
申请号：US12787929
申请日：2010-05-26
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/42356 , H01L29/42392 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/78618 , H01L29/78642
摘要： Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar.
摘要翻译：提供了能够防止由于泄漏电流的增加而导致的SGT（即三维半导体晶体管）的功耗的增加的半导体器件。半导体器件包括：第一导电型第一硅柱：围绕第一硅柱的侧表面的第一电介质; 围绕电介质的栅极; 设置在第一硅柱下方的第二硅柱; 以及设置在第一硅柱的顶部上的第三硅柱。第二硅柱具有形成在其表面上的第二导电型高浓度杂质区，除了与第一硅柱的接触表面区域的至少一部分以及形成在其中的第一导电型杂质区域第二导电型高浓度杂质区。第三硅柱具有形成在其表面上的第二导电型高浓度杂质区域，除了与第一硅柱的接触表面区域的至少一部分以及形成在其中的第一导电型杂质区域第三硅柱的第二导电型高浓度杂质区。第二硅柱和第三硅柱中的每一个的第一导电型杂质区的长度大于从相应的一个的第二导电型杂质区的第二导电型高浓度杂质区的基极部延伸的耗尽层的长度第二硅柱和第三硅柱。

27. 发明申请

US20100207200A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100207200A1
公开(公告)日：2010-08-19
申请号：US12704306
申请日：2010-02-11
申请人： Fujio Masuoka , Tomohiko Kudo
发明人： Fujio Masuoka , Tomohiko Kudo
IPC分类号： H01L29/78
CPC分类号： H01L29/42356 , H01L29/0657 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/7827
摘要： It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region (510) formed in a part of a first-conductive type semiconductor substrate (100), a first silicon pillar (810) of an arbitrary cross-sectional shape formed on the second-conductive type impurity region, a first insulating body (310) surrounding a part of a surface of the first silicon pillar, a gate (210) surrounding the first insulating body, and a second silicon pillar (820) which is formed on the first silicon pillar and which includes a second-conductive type impurity region (540). The gate is disposed to be separated from the semiconductor substrate by a second insulating body and is disposed to be separated from the second silicon pillar by the second insulating body. The capacitance between the gate and the semiconductor substrate is less than a gate capacitance, and the capacitance between the gate and the second silicon pillar is less than the gate capacitance.
摘要翻译：旨在解决由于作为三维半导体器件的周围栅晶体管（SGT）的寄生电容的增加而导致的功耗增加和操作速度的降低的问题，以提供实现增加速度的SGT 半导体电路的功耗降低。半导体器件包括形成在第一导电型半导体衬底（100）的一部分中的第二导电型杂质区（510），形成在第二导电类型半导体衬底上的任意截面形状的第一硅柱（810）围绕第一硅柱的表面的一部分的第一绝缘体（310），围绕第一绝缘体的栅极（210）和形成在第一硅柱上的第二硅柱（820）并且其包括第二导电型杂质区（540）。栅极被设置成通过第二绝缘体与半导体衬底分离，并且被设置成通过第二绝缘体与第二硅柱分离。栅极和半导体衬底之间的电容小于栅极电容，并且栅极和第二硅柱之间的电容小于栅极电容。

28. 发明授权

US06853037B2 Fabrication of low power CMOS device with high reliability 失效
标题翻译：制造具有高可靠性的低功耗CMOS器件
公开(公告)号：US06853037B2
公开(公告)日：2005-02-08
申请号：US09872007
申请日：2001-06-04
申请人： Tomohiko Kudo , Naohiko Kimizuka
发明人： Tomohiko Kudo , Naohiko Kimizuka
IPC分类号： H01L27/092 , H01L21/316 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/8238
摘要： A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films which is thicker than that of the lower threshold level MOSFET and, in addition, the gate oxide film of the higher threshold level MOSFET of n-type is thicker than that of the higher threshold level MOSFET of p-type. To fabricate the semiconductor device, implantation treatments of fluorine ions are carried out before the gate oxide treatment. Specifically, as for the higher threshold level MOSFETs of n- and p-types, implantation treatments of fluorine ions are independently carried out with unique implantation conditions.
摘要翻译：半导体器件包括相对较低的阈值电平MOSFET和n型和p型相对较高的阈值级MOSFET。较高阈值电平的MOSFET具有比下限阈值MOSFET厚的栅极氧化膜，此外，n型较高阈值电平MOSFET的栅极氧化膜比较高阈值电平MOSFET的栅极氧化膜厚 p型。为了制造半导体器件，在栅氧化物处理之前进行氟离子的注入处理。具体来说，对于n型和p型的较高阈值电平的MOSFET，独立的注入条件独立地进行氟离子的注入处理。

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