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    • 24. 发明申请
    • Transistor structure with dual trench for optimized stress effect and method therefor
    • 具有双沟槽的晶体管结构,用于优化应力效应及其方法
    • US20060091461A1
    • 2006-05-04
    • US10977266
    • 2004-10-29
    • Jian ChenMichael TurnerJames Vasek
    • Jian ChenMichael TurnerJames Vasek
    • H01L27/12H01L21/84
    • H01L21/76283H01L21/0274H01L21/823807H01L21/823878H01L21/84H01L27/1203H01L29/045H01L29/7842
    • A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a or semiconductor-on-insulator substrate.
    • 用于形成半导体器件结构的一部分的方法包括提供具有半导体有源层,绝缘层和半导体衬底的绝缘体上半导体衬底。 第一隔离沟槽形成在半导体有源层内,并且应力源材料沉积在第一沟槽的底部上,其中应力源材料包括双重用途的膜。 第二隔离沟槽形成在半导体有源层内,其中第二隔离沟槽不存在第二沟槽底部上的应力源材料。 在第一和第二隔离沟槽中分别存在和不存在应力材料提供差分应力:(i)在半导体器件结构的一个或多个N型或P型器件中,(ii)对于一个或多个 的宽度方向或沟道方向取向,以及(iii)定制绝缘体上半导体衬底中的一个或多个的应力益处。