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21. 发明授权

US07440531B2 Dynamic recalibration mechanism for elastic interface 失效
标题翻译：弹性界面的动态重新校准机制
公开(公告)号：US07440531B2
公开(公告)日：2008-10-21
申请号：US11055865
申请日：2005-02-11
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Gary A. Peterson , Robert J. Reese
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Gary A. Peterson , Robert J. Reese
IPC分类号： H04L25/00
CPC分类号： H04L7/005 , G11C19/287 , H03K5/133 , H03K2005/00058 , H04L7/0338
摘要： A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wrap around eye tracking.
摘要翻译：公开了一种用于使在弹性接口总线上接收的数字数据去偏斜和对准的方法和装置。在接收到数据后，通过可编程延迟线发送。在可编程延迟线中，数据在数据眼图中的三个点进行采样。动态调整三个采样点，以最大化数据眼图的覆盖范围。在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在采样器中的延迟调整时从功能采样器采样。在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。所述方法和装置允许替代眼睛跟踪并包裹眼睛跟踪。

22. 发明申请

US20100005349A1 ENHANCED MICROPROCESSOR INTERCONNECT WITH BIT SHADOWING 有权
标题翻译：增强微处理器互连与位冲洗
公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率率一段时间。响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

23. 发明授权

US08082474B2 Bit shadowing in a memory system 失效
标题翻译：存储系统中的位阴影
公开(公告)号：US08082474B2
公开(公告)日：2011-12-20
申请号：US12165799
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare Shadow counters are used to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。此外，阴影比较逻辑用于将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较阴影计数器用于计算相对于总线错误的误比率率一段时间。响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

24. 发明授权

US08050174B2 Self-healing chip-to-chip interface 失效
公开(公告)号：US08050174B2
公开(公告)日：2011-11-01
申请号：US12886404
申请日：2010-09-20
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

25. 发明授权

US07230449B2 Data receiver with a programmable reference voltage to optimize timing jitter 失效
标题翻译：具有可编程参考电压的数据接收器，以优化定时抖动
公开(公告)号：US07230449B2
公开(公告)日：2007-06-12
申请号：US11055805
申请日：2005-02-11
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Robert J. Reese , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Robert J. Reese , Glen A. Wiedemeier
IPC分类号： H03K17/16 , H04B3/00 , H04L25/00
CPC分类号： H04L25/0292 , G06F13/4072 , H04L7/0033 , H04L25/0272
摘要： Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.
摘要翻译：伪差分驱动器和接收器用于在两个或更多个IC芯片之间传送数据信号。使用可编程延迟电路对数据路径进行对齐，以使每个数据路径发生偏移。可编程参考发生器用于产生一个或一组接收机使用的参考电压，以检测数据信号。参考电压可以使用粗调以及精细的数字控制电压增量进行调节。测试信号从驱动器发送到接收器，并且参考电压在其可调节范围内使用粗略和精细调节控制来改变，而电路确定测试信号的连续转换时的检测定时抖动的量度。将参考电压的操作值设定为检测定时抖动确定为最小的值。

26. 发明授权

US08004335B2 Phase interpolator system and associated methods 有权
标题翻译：相位插值器系统及相关方法
公开(公告)号：US08004335B2
公开(公告)日：2011-08-23
申请号：US12028973
申请日：2008-02-11
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps , Frank D. Ferraiolo
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps , Frank D. Ferraiolo
IPC分类号： H03H11/16
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译：公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。

27. 发明申请

US20100109700A1 ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES 有权
标题翻译：电源漏电检测
公开(公告)号：US20100109700A1
公开(公告)日：2010-05-06
申请号：US12684142
申请日：2010-01-08
申请人： Frank D. Ferraiolo , Anuja Sehgal , Peilin Song , Michael A. Sperling
发明人： Frank D. Ferraiolo , Anuja Sehgal , Peilin Song , Michael A. Sperling
IPC分类号： G01R31/36
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.
摘要翻译：片上传感器检测电源漏洞。片内传感器采用敏感延迟链和不敏感延迟链，以检测电源下冲和过冲，而无需外部片外部件。检测到用户定义的阈值之外的下冲和超调。下冲和过冲由两个延迟链的相位相对差异表示。两个延迟链可编程，以检测各种频率。

28. 发明申请

US20090094476A1 DERIVING CLOCKS IN A MEMORY SYSTEM 失效
标题翻译：在记忆系统中传送时钟
公开(公告)号：US20090094476A1
公开(公告)日：2009-04-09
申请号：US12332396
申请日：2008-12-11
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00 , G06F1/06
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。该方法包括在集线器设备处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

29. 发明授权

US07279949B2 Programmable delay element 有权
标题翻译：可编程延迟元件
公开(公告)号：US07279949B2
公开(公告)日：2007-10-09
申请号：US11215416
申请日：2005-08-30
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Daniel J. Friedman , Seongwon Kim , Hector Saenz , Michael A. Sperling
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Daniel J. Friedman , Seongwon Kim , Hector Saenz , Michael A. Sperling
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00039
摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.
摘要翻译：公开了具有无毛刺操作的延迟元件和延迟线。作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

30. 发明授权

US06930507B2 Thevenins receiver 失效
标题翻译：戴维宁接收器
公开(公告)号：US06930507B2
公开(公告)日：2005-08-16
申请号：US10616845
申请日：2003-07-10
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/0296
摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.
摘要翻译：终端网络具有多个电阻器，其形成具有公共节点的多个分压器。一半的电阻器与P沟道场效应晶体管（PFET）耦合到正电源电压，另一半电阻与N沟道FET（NFET）耦合到负极或接地电源电压。逻辑信号用于控制FET的栅极。通过修改哪些FET为ON，可以选择性地控制终端网络以产生具有相同阻抗水平的各种偏移电平。阻抗水平也可以被修改，同时保持相同的偏移水平。可以选择性地采用延迟电路来在所选择的延迟时间之后反馈控制信号以调整阈值电平以动态地或静态地优化信号接收。

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