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21. 发明授权

US06867194B2 Enzyme activated nitric oxide donors 失效
标题翻译：酶活化一氧化氮供体
公开(公告)号：US06867194B2
公开(公告)日：2005-03-15
申请号：US09925816
申请日：2001-08-09
申请人： Peng George Wang , Xuejun Wu , Xiaoping Tang
发明人： Peng George Wang , Xuejun Wu , Xiaoping Tang
IPC分类号： A61K31/706 , C07H13/12 , A61K3/785
CPC分类号： C07H13/12 , A61K31/706
摘要： Sugar-modified SIN-1 compositions are provided. The compositions are useful for generating NO in response to hydrolytic activity of a glycosidase specific for the O-glycosidic bond between the sugar and SIN-1 moieties. Pharmaceutical compositions containing the sugar-modified SIN-1 compositions and methods of using the compositions are also provided.
摘要翻译：提供了糖改性的SIN-1组合物。该组合物可用于响应糖和SIN-1部分之间的O-糖苷键特异的糖苷酶的水解活性产生NO。还提供了含有糖修饰的SIN-1组合物的药物组合物和使用该组合物的方法。

22. 外观设计

USD1038189S1 Ice cube mould 有权
公开(公告)号：USD1038189S1
公开(公告)日：2024-08-06
申请号：US29938216
申请日：2024-04-19
申请人： Xiaoping Tang
设计人： Xiaoping Tang
摘要： FIG. 1 is a front perspective view of an ice cube mould, showing my new design;
FIG. 2 is a bottom perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof;
FIG. 8 is a bottom view thereof; and,
FIG. 9 is its usage state diagram.
The broken lines in the drawings illustrate the portions of the ice cube mould, which form no part of the claimed design.

23. 发明授权

US09889328B2 Connecting structure between trampoline bed and frame, and trampoline and connecting piece using same 有权
公开(公告)号：US09889328B2
公开(公告)日：2018-02-13
申请号：US15100524
申请日：2014-07-17
申请人： Xiaoping Tang
发明人： Zhendong Dai , Xiaoping Tang
IPC分类号： A63B5/11 , A63B21/055
CPC分类号： A63B5/11 , A63B21/0552 , A63B21/0557 , A63B2225/09
摘要： A connecting structure between a jumping mat and a frame in a trampoline, comprises an elastic element connected to the frame, the elastic element having at least one positioning element; and a connecting element connected to the jumping mat, the connecting element having at least one limiting element for engaging one of the plurality of positioning elements and thus connecting the elastic element to the connecting element. A trampoline using the connecting structure is also disclosed.

24. 发明申请

US20160296782A1 Connecting Structure Between Trampoline Bed and Frame, and Trampoline and Connecting Piece Using Same 有权
标题翻译：蹦床床架与蹦床与连接件之间的连接结构使用相同
公开(公告)号：US20160296782A1
公开(公告)日：2016-10-13
申请号：US15100524
申请日：2014-07-17
申请人： Xiaoping TANG
发明人： Zhendong Dai , Xiaoping Tang
IPC分类号： A63B5/11 , A63B21/055
CPC分类号： A63B5/11 , A63B21/0552 , A63B21/0557 , A63B2225/09
摘要： A connecting structure between a jumping mat and a frame in a trampoline, comprises an elastic element connected to the frame, the elastic element having at least one positioning element; and a connecting element connected to the jumping mat, the connecting element having at least one limiting element for engaging one of the plurality of positioning elements and thus connecting the elastic element to the connecting element. A trampoline using the connecting structure is also disclosed.
摘要翻译：蹦床中的跳床和框架之间的连接结构包括连接到框架的弹性元件，弹性元件具有至少一个定位元件; 以及连接到所述跳跃垫的连接元件，所述连接元件具有用于接合所述多个定位元件中的一个的至少一个限制元件，从而将所述弹性元件连接到所述连接元件。还公开了一种使用连接结构的蹦床。

25. 发明申请

US20130263068A1 RELATIVE ORDERING CIRCUIT SYNTHESIS 有权
标题翻译：相关订购电路合成
公开(公告)号：US20130263068A1
公开(公告)日：2013-10-03
申请号：US13431368
申请日：2012-03-27
申请人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
发明人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.
摘要翻译：本文提供了相对排序电路合成的系统和方法。一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。本文还描述了其它实施例和方面。

26. 发明授权

US08302062B2 Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization 有权
标题翻译：在分层电路布局优化中获得可行整数解的方法
公开(公告)号：US08302062B2
公开(公告)日：2012-10-30
申请号：US12712880
申请日：2010-02-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

27. 发明授权

US07761818B2 Obtaining a feasible integer solution in a hierarchical circuit layout optimization 失效
标题翻译：在分层电路布局优化中获得可行的整数解
公开(公告)号：US07761818B2
公开(公告)日：2010-07-20
申请号：US11782706
申请日：2007-07-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

28. 发明申请

US20100153892A1 METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 有权
标题翻译：在分层电路布局优化中获得可行整数解的方法
公开(公告)号：US20100153892A1
公开(公告)日：2010-06-17
申请号：US12712880
申请日：2010-02-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

29. 发明申请

US20090031259A1 OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 失效
标题翻译：在分层电路布局优化中获得可行的整数解
公开(公告)号：US20090031259A1
公开(公告)日：2009-01-29
申请号：US11782706
申请日：2007-07-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

30. 发明授权

US07437691B2 VLSI artwork legalization for hierarchical designs with multiple grid constraints 有权
标题翻译：用于具有多个网格约束的分层设计的VLSI艺术品合法化
公开(公告)号：US07437691B2
公开(公告)日：2008-10-14
申请号：US11279283
申请日：2006-04-11
申请人： Xiaoping Tang , Xin Yuan
发明人： Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F17/504 , G06F17/5068 , G06F2217/06
摘要： A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ground rule correct, the system and method provide a legalized layout which meets the multiple grid constraints while maintaining LVS correctness and fixing the ground rule errors as much as possible with minimum layout perturbation from the input design. The system and method support multiple grid pitch constraints for hierarchical design, and provide for LVS correctness to be maintained while an on-grid solution possibly with some spacing violations.
摘要翻译：公开了一种用于使平坦或分级VLSI布局合法化以满足多个网格约束和常规基本规则的系统和方法。给定一组具有多个网格约束的基本规则和布局与原理图（LVS）的VLSI布局（分层或平面）正确但可能不是基本规则正确的，系统和方法提供了合法化的布局，满足多个网格约束，同时保持LVS的正确性，并尽可能多地修正接地规则错误，并从输入设计中获得最小的布局扰动。该系统和方法支持用于分级设计的多个网格间距约束，并且在可能具有一些间隔违规的并网解决方案时提供要维护的LVS正确性。

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