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21. 发明授权

US09673229B2 Array substrate, method for manufacturing the same and display apparatus 有权
公开(公告)号：US09673229B2
公开(公告)日：2017-06-06
申请号：US15177795
申请日：2016-06-09
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Jinchao Bai , Yao Liu , Liangliang Li , Zhaohui Hao , Liang Sun
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L27/12 , G02F1/1368 , G02F1/1362 , G02F1/1345 , G02F1/1333 , H01L23/31 , G02F1/1343
CPC分类号： H01L27/124 , G02F1/133345 , G02F1/1345 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2201/121 , G02F2201/123 , G02F2201/40 , H01L23/3171 , H01L27/1214 , H01L27/1218 , H01L27/1248
摘要： An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode (2) and a pixel electrode (10) sequentially formed on the substrate (1) and insulated from each other; a thin film transistor comprising a gate electrode (4), an active layer (7), a source electrode (8a) and a drain electrode (8b), wherein the drain electrode (8b) is electrically connected with the pixel electrode (10); a common electrode line (5) disposed in a same layer as the gate electrode (4); and an insulating layer (3) between the gate electrode (4) and the common electrode (2), wherein the common electrode (2) is connected with the common electrode line (5) through a through hole in the insulating layer (3).

22. 发明授权

US10324553B2 Array substrate and fabrication method thereof, optical touch screen, and display device 有权
公开(公告)号：US10324553B2
公开(公告)日：2019-06-18
申请号：US15327767
申请日：2016-03-24
申请人： Boe Technology Group Co., Ltd. , Beijing Boe Display Technology Co., Ltd.
发明人： Jinchao Bai , Tsungchieh Kuo , Xiangqian Ding , Yao Liu , Xiaowei Liu , Xi Chen
IPC分类号： G06F3/041 , G06F3/042 , G02F1/1333 , G02F1/1362 , G02F1/1368 , H01L27/144
摘要： Disclosed is an array substrate including a base substrate and a gate metal layer, a semiconductor layer, a source-drain metal layer, and a pixel electrode layer that are formed on the base substrate. The gate metal layer includes gate lines, gate electrodes of thin film transistors, and a plurality of first sensing lines extending along a row direction. The semiconductor layer includes an active layer of the thin film transistors, and a plurality of first photosensitive elements and a plurality of second photosensitive elements that are insulated from each other. The source-drain metal layer includes data lines, source electrodes and drain electrodes of the thin film transistors, and a plurality of second sensing lines extending along a column direction. Also disclosed are a method of fabricating the array substrate, an optical touch screen and a display device.

23. 发明授权

US10014329B2 Array substrate with thin film transistor and method of manufacturing the same 有权
公开(公告)号：US10014329B2
公开(公告)日：2018-07-03
申请号：US14436843
申请日：2014-09-11
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Jinchao Bai , Xiangqian Ding , Yao Liu , Liangliang Li , Zongjie Guo
IPC分类号： H01L27/12 , H01L29/66 , H01L29/78 , G02F1/13
CPC分类号： H01L27/1248 , H01L27/124 , H01L27/127 , H01L27/1288
摘要： An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.

24. 发明申请

US20160233247A1 Array Substrate and Manufacturing Method Thereof, and Display Device 有权
标题翻译：阵列基板及其制造方法及显示装置
公开(公告)号：US20160233247A1
公开(公告)日：2016-08-11
申请号：US14738358
申请日：2015-06-12
申请人： BOE Technology Group Co., Ltd. , Beijing BOE Display Technology Co., Ltd.
发明人： Jinchao Bai , Zongjie Guo , Xiangqian Ding , Xiaowei Liu , Yao Liu
IPC分类号： H01L27/12 , H01L29/45 , H01L29/49 , G02F1/1368 , G02F1/1362
CPC分类号： H01L29/45 , G02F1/1345 , G02F1/136286 , H01L27/124 , H01L27/1288
摘要： An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region sequentially includes a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode; the peripheral circuit region sequentially includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer. An orthogonal projection area of the second circuit line is at least partly overlapped with an orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer. A method for manufacturing the array substrate and a display device including the array substrate are also disclosed.
摘要翻译：公开了一种包括基底基板的阵列基板; 基底基板被分成像素区域和外围电路区域，像素区域依次包括栅电极，栅极绝缘层，半导体有源层，像素电极，源极/漏极，钝化层和共同的电极; 外围电路区域依次包括第一电路线，栅绝缘层，第二电路线和钝化层。第二电路线的正交投影区域至少部分地与基底基板上的第一电路线的正交投影区域重叠，并且第二电路线通过穿过栅极的通孔与第一电路线直接电连接绝缘层。还公开了阵列基板的制造方法和包括阵列基板的显示装置。

25. 发明申请

US20150323483A1 DETECTION DEVICE 有权
标题翻译：检测装置
公开(公告)号：US20150323483A1
公开(公告)日：2015-11-12
申请号：US14496062
申请日：2014-09-25
申请人： Boe Technology Group Co., Ltd.
发明人： Xiaowei Liu , Yao Liu , Xiangqian Ding , Jinchao Bai
IPC分类号： G01N27/22 , C23C16/44 , C23C16/455
CPC分类号： C23C16/52 , C23C2/14 , C23C14/545 , C23C14/564 , C23C16/4401 , C23C16/45589 , C23C16/45591 , G01B7/085 , G01B7/105 , G01N27/228 , G01R27/26 , H01J37/32568 , H01L21/67253
摘要： A detection device includes a chamber for vacuum coating, a capacitance measurement device and a baffle mechanism located in the chamber. The baffle mechanism is a closed structure encompassed by a number of baffle walls, wherein at least one baffle wall includes a fixed baffle plate and a moveable baffle plate. The moveable baffle plate is pivotable about the fixed baffle plate. The moveable baffle plate, after pivoting, may get parallel with an adjacent baffle wall. The adjacent baffle wall and the moveable baffle plate are respectively connected to the capacitance measurement device, and the capacitance measurement device is used to measure the capacitance between the adjacent baffle wall and the moveable baffle plate. The detection device may accurately detect the service life of the baffle mechanism and achieve precise management of the apparatus.
摘要翻译：检测装置包括用于真空涂覆的室，电容测量装置和位于室中的挡板机构。挡板机构是由多个挡板包围的封闭结构，其中至少一个挡板壁包括固定挡板和可移动挡板。可移动挡板可围绕固定挡板枢转。可移动挡板在枢转之后可能与相邻的挡板平行。相邻的挡板壁和可动挡板分别连接到电容测量装置，并且电容测量装置用于测量相邻挡板壁和可移动挡板之间的电容。检测装置可以准确地检测挡板机构的使用寿命，实现设备的精确管理。

26. 发明申请

US20150277197A1 ARRAY SUBSTRATE, METHOD FOR REPAIRING THE SAME AND DISPLAY APPARATUS 审中-公开
标题翻译：阵列基板，其修复方法和显示装置
公开(公告)号：US20150277197A1
公开(公告)日：2015-10-01
申请号：US14316039
申请日：2014-06-26
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Xi Chen , Guoqi Mao , Liangliang Li , Yao Liu
IPC分类号： G02F1/1362 , G02F1/1368
CPC分类号： G02F1/136259 , G02F2001/136263
摘要： An array substrate, a method for repairing the same and a display apparatus are disclosed. The array substrate, comprises: a plurality of first signal lines and a plurality of second signal lines; a plurality of pixel units each comprising a thin film transistor and a pixel electrode; and connecting assemblies comprising a plurality of first portions arranged in the layer in which the second signal lines are located and a plurality of second portions arranged in the layer in which the pixel electrodes are located, the first signal lines, the second signal lines and the pixel electrodes being in different layers on the array substrate respectively, the first portions and the second portions in the connecting assemblies being arranged alternatively, the plurality of first portions being partly overlapped with the first signal lines respectively, the second portions being partly overlapped with adjacent first portions.
摘要翻译：公开了阵列基板，其修补方法和显示装置。阵列基板包括：多条第一信号线和多条第二信号线; 多个像素单元，每个像素单元包括薄膜晶体管和像素电极; 以及连接组件，包括布置在第二信号线所在的层中的多个第一部分和布置在像素电极所在的层中的多个第二部分，第一信号线，第二信号线和像素电极分别位于阵列基板上的不同层中，连接组件中的第一部分和第二部分交替布置，多个第一部分分别与第一信号线部分重叠，第二部分与相邻部分重叠第一部分。

27. 发明授权

US09146431B2 Array substrate, method for manufacturing the same and display apparatus 有权
标题翻译：阵列基板，其制造方法和显示装置
公开(公告)号：US09146431B2
公开(公告)日：2015-09-29
申请号：US13976498
申请日：2012-11-12
申请人： BOE Technology Group Co., Ltd. , Beijing BOE Display Technology Co., Ltd.
发明人： Jinchao Bai , Yao Liu , Liangliang Li , Zhaohui Hao , Liang Sun
IPC分类号： H01L21/00 , G02F1/1345 , G02F1/1362 , H01L27/12 , G02F1/1368 , G02F1/1343
CPC分类号： H01L27/124 , G02F1/133345 , G02F1/1345 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2201/121 , G02F2201/123 , G02F2201/40 , H01L23/3171 , H01L27/1214 , H01L27/1218 , H01L27/1248
摘要： An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode (2) and a pixel electrode (10) sequentially formed on the substrate (1) and insulated from each other; a thin film transistor comprising a gate electrode (4), an active layer (7), a source electrode (8a) and a drain electrode (8b), wherein the drain electrode (8b) is electrically connected with the pixel electrode (10); a common electrode line (5) disposed in a same layer as the gate electrode (4); and an insulating layer (3) between the gate electrode (4) and the common electrode (2), wherein the common electrode (2) is connected with the common electrode line (5) through a through hole in the insulating layer (3).
摘要翻译：提供阵列基板，其制造方法和显示装置。阵列基板包括：基板（1）; 依次形成在所述基板（1）上并且彼此绝缘的公共电极（2）和像素电极（10）; 包括栅极（4），有源层（7），源电极（8a）和漏电极（8b）的薄膜晶体管，其中漏电极（8b）与像素电极（10）电连接， ; 设置在与栅电极（4）相同的层中的公共电极线（5）; 以及在所述栅电极（4）和所述公共电极（2）之间的绝缘层（3），其中所述公共电极（2）通过所述绝缘层（3）中的通孔与所述公共电极线（5）连接，。

28. 发明授权

US08962404B2 Method for manufacturing fan-out lines on array substrate 有权
标题翻译：在阵列基板上制造扇出线的方法
公开(公告)号：US08962404B2
公开(公告)日：2015-02-24
申请号：US14077770
申请日：2013-11-12
申请人： Boe Technology Group Co., Ltd. , Beijing Boe Display Technology Co., Ltd.
发明人： Jinchao Bai , Liang Sun , Xiangqian Ding , Liangliang Li , Yao Liu
IPC分类号： H01L21/00 , H01L27/12
CPC分类号： H01L27/1288 , H01L27/124 , H01L27/127 , H01L29/66765
摘要： A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; forming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines.
摘要翻译：公开了一种在阵列基板上制造扇出线的方法。扇出线包括非晶硅层，欧姆接触层和设置在栅极绝缘层上的源极 - 漏极电极层。可以通过在源极 - 漏极电极层上形成第一层光致抗蚀剂并在第一层光致抗蚀剂上进行半曝光显影处理来进行制造工艺; 通过蚀刻工艺蚀刻非晶硅层，欧姆接触层和源极 - 漏极电极层; 去除第一层光刻胶; 形成第二层光致抗蚀剂并在第二层光致抗蚀剂上进行全曝光显影处理; 并通过蚀刻工艺蚀刻非晶硅层以形成扇出线。

29. 发明授权

US09904392B2 Touch display screen, a manufacturing method thereof and a display device 有权
公开(公告)号：US09904392B2
公开(公告)日：2018-02-27
申请号：US15511588
申请日：2016-04-12
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Kui Liang , Bin Feng , Yao Liu
IPC分类号： G06F3/041 , G02F1/1343
CPC分类号： G06F3/0412 , G02F1/13338 , G02F1/1343 , G06F3/044 , G06F2203/04103
摘要： This disclosure discloses a touch display screen, a manufacturing method thereof and a display device. The touch display screen comprises: an opposite substrate, an array substrate, and a liquid crystal layer located between the opposite substrate and the array substrate, a side of the opposite substrate facing the liquid crystal layer being provided with a black matrix. The touch display screen further comprises: a first touch electrode, an insulating layer and a second touch electrode arranged in stack successively at a side of the opposite substrate back to the liquid crystal layer. The first touch electrode and the second touch electrode are located within an area corresponding to the black matrix respectively. The first touch electrode comprises a plurality of first touch sub-electrodes distributed along a first direction. The second touch electrode comprises a plurality of second touch sub-electrodes distributed along a second direction perpendicular to the first direction.

30. 发明申请

US20180031896A1 ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20180031896A1
公开(公告)日：2018-02-01
申请号：US15726995
申请日：2017-10-06
申请人： BOE Technology Group Co, Ltd. , Beijing BOE Display Technology Co, Ltd.
发明人： Xiaowei Liu , Xi Chen , Zhenfei Cai , Yao Liu , Liangliang Li , Zongjie Guo
IPC分类号： G02F1/1345 , H01L27/12 , H01L21/768
CPC分类号： G02F1/13458 , G02F2001/13456 , H01L21/768 , H01L27/124 , H01L27/1248 , H01L27/1259
摘要： The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

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